Semiconductor Memory Fabrication Using Capping Layer Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of forming memory cells and peripheral circuitry on integrated semiconductor circuits complicates the fabrication process, especially as circuits become more complex and compact, necessitating a simplified method for forming signal transmission conductive layers in both cell array and peripheral regions.
Innovation Solution
A method involving the preparation of a semiconductor substrate divided into cell array and peripheral regions, with a lower layer forming a cell array signal transmission conductive layer, followed by the formation of insulation and capping layers, etching to expose the lower layer, and the creation of stopper and insulation mold layers to simplify the fabrication process, including dry etching and the use of materials like silicon nitride for the capping layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional fabrication methods are used to form signal transmission conductive layers in both cell array and peripheral regions, then electrical connectivity is achieved, but the fabrication process becomes overly complex and time-consuming
Solution Approach 1:
The patent merges the formation of cell array signal transmission conductive layers and peripheral region signal transmission conductive layers into a single integrated process. The insulation layer is formed across the entire substrate, and the capping layer is deposited uniformly, allowing simultaneous processing of both regions. This eliminates the need for separate fabrication steps for different regions, directly reducing process complexity while maintaining electrical connectivity requirements.
Solution Approach 2:
The capping layer serves multiple functions: it protects the insulation layer and conductive layers, provides a uniform surface for subsequent processing, and enables simultaneous access to lower layers in both cell array and peripheral regions. This multi-functional approach simplifies the overall fabrication process by eliminating the need for region-specific processing steps.
2Productivity
If multiple separate layers and steps are used to form conductive layers in different regions, then electrical connectivity is ensured, but manufacturing time and process steps increase
Solution Approach 1:
The patent implements continuous fabrication actions where the insulation layer is deposited across the entire substrate in one step, followed by uniform capping layer deposition. The etching process then simultaneously exposes lower layers in both cell array and peripheral regions through a single continuous operation. This eliminates idle time between steps and maintains continuous productive action throughout the fabrication sequence.
Solution Approach 2:
The insulation layer is formed in advance across the entire substrate before any region-specific processing is needed. This preliminary action creates a unified foundation that enables subsequent simultaneous processing of multiple regions, reducing the need for repeated layer formation steps and accelerating overall fabrication.
3Ease of manufacture
If region-specific processing steps are used for cell array and peripheral regions, then functional requirements are met, but the number of fabrication steps increases
Solution Approach 1:
The patent combines the processing of cell array and peripheral regions into unified fabrication steps. The same insulation layer formation, capping layer deposition, and etching processes are applied simultaneously to both regions, reducing the total number of distinct process steps while still meeting the different functional requirements of each region through selective patterning and material removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the fabrication of semiconductor memory devices by reducing the step height between cell and peripheral regions, facilitating further processing and improving the integration of signal transmission conductive layers, thereby enhancing the efficiency of memory device production.
Implementation Method 1
etching the capping layer so that the lower layer of the cell array region is exposed
Implementation Method 2
the etching of the capping layer may include dry etching
Data Source
AI summary
A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.