Semiconductor Memory Cell Array Vertical Stacking for Pitch Reduction
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Solution Overview
Problem
In semiconductor manufacturing, narrowing the formation pitch between nonvolatile memory elements to reduce the area of the nonvolatile memory cell array can lead to short circuits and damage to underlying components due to residue redeposition during etching, and excessive etching is required to prevent short circuits, which may damage wiring and selection transistors.
Innovation Solution
A semiconductor apparatus with a nonvolatile memory cell array configuration where first and second memory elements are arranged in a two-dimensional matrix on the same interlayer insulating layer, with the first memory element being larger than the second, and disposed adjacent to each other, allowing for reduced formation pitches without short circuits, and a method for manufacturing this apparatus involving the formation and patterning of stack films for the memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the formation pitch between nonvolatile memory elements is narrowed to reduce the area of the nonvolatile memory cell array, then the area is reduced, but short circuits and damage to underlying components occur due to residue redeposition during etching
Solution Approach 1:
The patent introduces a third dimension by forming the first memory element at a different height level than the second memory element. Specifically, the first memory element is formed on a first interlayer insulating layer while the second memory element is formed on a second interlayer insulating layer at a higher level. This vertical separation in the z-direction allows the formation pitch in the planar direction to be reduced without causing short circuits, as residues from etching one element will not redeposit on the other element due to the height difference.
2Reliability
If excessive etching is performed to prevent short circuits, then short circuit prevention is improved, but damage to wiring and selection transistors occurs
Solution Approach 1:
By forming memory elements at different height levels using multiple interlayer insulating layers, the patent enables moderate etching conditions to be used without causing short circuits. The vertical separation provides inherent isolation, eliminating the need for excessive etching that would damage underlying wiring and selection transistors.
3Length of moving object
If the interval between adjacent nonvolatile memory elements is reduced, then the formation pitch is reduced, but residue redeposition during etching causes short circuits
Solution Approach 1:
The patent resolves the manufacturing precision issue by utilizing vertical dimensionality. Memory elements are formed at different heights using stacked interlayer insulating layers, which prevents residue redeposition from causing short circuits even when the horizontal interval between elements is minimized. This allows the formation pitch to be reduced while maintaining manufacturing precision.
Data Source
AI summary
A semiconductor apparatus includes a nonvolatile memory cell array including a plurality of first memory cells and a plurality of second memory cells including a first memory element 11 and a second memory element 12 including a resistance-variable nonvolatile memory element and a first selection transistor electrically connected to the first memory element 11 and the second memory element 12, in which a plurality of first memory elements 11 and a plurality of second memory elements 12 are arranged in a two-dimensional matrix in a first direction and a second direction different from the first direction and on the same interlayer insulating layer, the first memory element 11 is larger than the second memory element 12, and the first memory element 11 and the second memory element 12 are disposed adjacent to each other along the second direction.