Semiconductor Memory Cell With Back Gate Oxide Transistor for Low Leakage
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Solution Overview
Problem
Current semiconductor devices, such as DRAM and flash memory, face limitations in data retention, power consumption, and durability due to high leakage currents and the need for frequent refresh operations, especially in volatile storage devices, and are not suitable for applications requiring frequent data rewriting.
Innovation Solution
A semiconductor device with a memory cell structure using a writing transistor and a reading transistor, both incorporating oxide semiconductors, which reduces the need for refresh operations, allows for low-power operation, and enables high-speed data storage and retrieval without limitations on the number of writing cycles, utilizing a back gate electrode and specific wiring connections to manage data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a DRAM structure is used to achieve high-speed writing, then writing speed is improved, but data retention time deteriorates due to short holding time and leakage current
Solution Approach 1:
The invention divides the transistor into two separate transistors: a first transistor for high-speed writing operations and a second transistor for data holding. This segmentation allows each transistor to be optimized for its specific function, resolving the contradiction between writing speed and data retention time
Solution Approach 2:
The invention introduces a new dimension by adding a back gate electrode to the second transistor, enabling independent control of the channel thickness. This additional control dimension allows the second transistor to maintain extremely low leakage current while the first transistor provides high-speed writing capability
2Duration of action of stationary object
If a flip-flop circuit is used in SRAM to achieve long data holding time, then data retention is improved, but device complexity increases
Solution Approach 1:
The invention extracts the data holding function from complex flip-flop circuits and implements it using a simple transistor-capacitor structure with a back gate electrode. This extraction maintains long data holding time while dramatically reducing circuit complexity
Solution Approach 2:
The invention changes the control parameter by introducing back gate voltage control to adjust the threshold voltage of the second transistor. This parameter change enables the simple transistor-capacitor structure to achieve data holding performance comparable to complex flip-flop circuits
3Duration of action of stationary object
If flash memory structure is used to achieve nonvolatile storage, then data retention is improved, but writing durability deteriorates due to gate insulating layer deterioration
Solution Approach 1:
The invention uses a conventional gate insulating layer without the need for thick tunnel insulating layers required in flash memory. This allows the gate insulating layer to withstand repeated writing operations without deterioration, significantly improving writing durability while maintaining nonvolatile storage capability
Solution Approach 2:
The invention changes the electrical parameters by using a thin back gate insulating layer (5 nm to 50 nm) compared to thick tunnel insulating layers in flash memory. This parameter change enables low-voltage operation and repeated writing without gate insulating layer breakdown
4Duration of action of stationary object
If high voltage is applied to achieve charge holding in floating gate, then data retention is improved, but power consumption increases
Solution Approach 1:
The invention changes the voltage parameter by using low voltage (lower than 5 V) instead of high voltage for charge storage. The back gate electrode controls the threshold voltage to prevent leakage, achieving data retention without high-voltage tunneling current and thus reducing power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor device achieves long-term data retention, reduced power consumption, and increased storage capacity with stable and reliable operation, eliminating the need for frequent refresh operations and high-voltage writing, thus enhancing its suitability for applications requiring frequent data access.
Implementation Method 1
a reading transistor TRR including a back gate electrode... a gate electrode of the reading transistor is electrically connected to one of a source electrode and a drain electrode of the writing transistor
Implementation Method 2
both incorporating oxide semiconductors, which reduces the need for refresh operations... enables low-power operation
Data Source
AI summary
A semiconductor device with a reduced area and capable of higher integration and larger storage capacity is provided. A multi-valued memory cell including a reading transistor which includes a back gate electrode and a writing transistor is used. Data is written by turning on the writing transistor so that a potential according to the data is supplied to a node where one of a source electrode and a drain electrode of the writing transistor and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor and holding a predetermined potential in the node. Data is read by supplying a reading control potential to a control signal line connected to one of a source electrode and a drain electrode of the reading transistor, and then detecting potential change of a reading signal line.