Semiconductor Memory Cell With Dual-Width Selection Transistors
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices of the insulating-film breakdown type, also known as OTP memories, face challenges in reducing memory cell size and increasing storage capacity due to high voltage requirements and increased capacitance in data lines, which limits integration density and sense time.
Innovation Solution
The design incorporates a semiconductor memory device with a MOS structure, featuring a pMOS e-Fuse element and two selection transistors with different gate-electrode widths, where the second selection transistor has a smaller gate-electrode width, reducing data line capacitance and enabling faster data detection, and sharing sense amplifiers and control registers across columns to minimize area and enhance storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional OTP memory cell configuration is used with high voltage transistors for programming, then data can be stored in nonvolatile state, but the memory cell area increases and integration density decreases
Solution Approach 1:
The memory cell is segmented into two distinct transistor types: a first selection transistor with larger gate width for programming operations, and a second selection transistor with smaller gate width for sensing operations. This segmentation allows each transistor to be optimized for its specific function, reducing the overall memory cell area while maintaining nonvolatile data storage capability through the e-Fuse element
Solution Approach 2:
Different regions of the memory cell are assigned different transistor characteristics tailored to local functional requirements. The first selection transistor region is designed with larger gate width to handle high voltage programming, while the second selection transistor region uses smaller gate width for low-voltage sensing, optimizing both functions within a compact area
2Power
If data line capacitance is increased to drive high voltage for programming, then programming can be performed, but sense time increases and speed decreases
Solution Approach 1:
The memory cell dynamically switches between two operational modes using different selection transistors: programming mode uses the first selection transistor capable of handling high voltage to break down the insulating film, while sensing mode uses the second selection transistor with smaller gate width and lower capacitance for fast data detection, thereby achieving both high voltage programming and fast sensing
Solution Approach 2:
The memory cell alternates between programming operations requiring high voltage and sensing operations requiring fast response. The periodic switching between the two selection transistors allows the system to perform high voltage programming when needed, then quickly switch to the lower capacitance second transistor for rapid data sensing and reading
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the area and sense time required for each memory cell, allowing for a higher integration density and increased storage capacity in the OTP memory device.
Implementation Method 1
The e-Fuse element stores data '1' when the high voltage applied between its gate electrode and its source-drain terminal breaks down its gate-insulating film
Data Source
AI summary
A semiconductor memory device includes a memory element, a first data line and a second data line, a first selection transistor, and a second selection transistor. The memory element includes a semiconductor element of MOS structure in which data is programmed when an insulating film provided in the semiconductor element is broken down by application of a voltage thereto. The first and second data lines are connected to a sense amplifier. The first selection transistor is configured to connect the memory element to the first data line in order to program data in the memory element. The second selection transistor is configured to connect the memory element to the second data line in order to program data in the memory element and detect the data programmed in the memory element. The second selection transistor has a smaller gate-electrode width smaller than the first selection transistor.