Semiconductor Memory Cell Floating Body Gate Design
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Solution Overview
Problem
Current semiconductor memory devices either lose data when power is discontinued (volatile memory) or operate slowly (non-volatile memory), lacking a universal type that balances speed with data retention.
Innovation Solution
A semiconductor memory cell design incorporating a floating body and a floating gate or trapping layer that switches between volatile and non-volatile modes, allowing data transfer between the two when power is interrupted or restored, using a parallel, non-algorithmic process for efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory is used, then fast operation is achieved, but data is lost when power is discontinued
Solution Approach 1:
The patent combines volatile memory (floating body) and non-volatile memory (floating gate) into a single unified memory structure. The floating body provides fast volatile storage while the floating gate provides non-volatile retention, merging the advantages of both memory types in one device.
Solution Approach 2:
The memory device is designed to perform multiple functions: it can operate as volatile memory during powered states for fast access, and as non-volatile memory during power interruption for data retention. This multi-functionality allows a single device to satisfy both speed and retention requirements.
2Loss of information
If non-volatile memory is used, then data retention is achieved, but operation speed decreases
Solution Approach 1:
The patent merges non-volatile floating gate storage with volatile floating body storage, allowing the system to leverage the speed of volatile memory during normal operation while retaining the non-volatile capability through the floating gate structure.
Solution Approach 2:
The memory device dynamically switches between volatile and non-volatile modes based on power availability. During powered states, it operates in volatile mode for high speed; during power interruption, it transitions to non-volatile mode for data retention, making the performance characteristic dynamic rather than fixed.
3Adaptability or versatility
If a universal memory device combining both modes is created, then both speed and data retention are achieved, but device complexity increases
Solution Approach 1:
The patent merges the floating body and floating gate into a single integrated memory cell structure with shared source/drain regions and control circuits. This unified structure reduces overall device complexity compared to having separate volatile and non-volatile memory devices, while still providing both operational modes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables fast operation like volatile memory while retaining data like non-volatile memory, with parallel data transfer processes enhancing speed and efficiency, allowing the memory device to function as both volatile and non-volatile simultaneously.
Implementation Method 1
a first region embedded in the substrate at a first location of the substrate and having a second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory
Implementation Method 2
a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell
Implementation Method 3
when power to the cell is interrupted, data transfer from the floating body to the floating gate or trapping layer occurs and the floating gate or trapping layer stores the data as non-volatile memory
Data Source
AI summary
Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.