Semiconductor Memory Cell Layout With Vertical Active Body Stacking
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Solution Overview
Problem
The integration density of switch transistors in semiconductor structures is relatively low, limiting the number of memory cells that can be integrated in a given unit size, which affects the memory capacity.
Innovation Solution
A semiconductor structure is designed with multiple bit lines and word lines arranged in a specific configuration within an insulator on a base substrate, where each active body includes source and drain parts, and only one word line is placed between two adjacent active bodies, allowing for improved integration density by reducing the space between active bodies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional memory cell layout is used with word lines, bit lines, switch transistors, and capacitors integrated on the same semiconductor structure, then the memory structure can be simplified, but the integration density of switch transistors becomes relatively low
Solution Approach 1:
The patent transitions from planar integration to three-dimensional vertical integration by stacking multiple active bodies (source/drain regions) vertically above the base substrate. This dimensional change allows multiple memory cells to occupy the same footprint area, dramatically increasing integration density while maintaining the simplified monolithic structure.
Solution Approach 2:
The patent implements nesting by placing multiple active bodies (first active body, second active body, etc.) within the vertical space above the base substrate. Each active body is nested within the three-dimensional structure, with source and drain regions arranged in stacked configurations, allowing multiple transistors to occupy a compact volume.
2Quantity of substance
If more memory cells are integrated in a given unit size, then memory capacity increases, but the space between active bodies must be reduced
Solution Approach 1:
By moving from two-dimensional planar arrangement to three-dimensional vertical stacking, the patent reduces the horizontal space between active bodies while increasing vertical separation. Multiple active bodies are positioned at different heights above the base substrate, allowing denser packing without reducing the critical dimensional spacing needed for fabrication.
Data Source
AI summary
A semiconductor structure includes: a base substrate; an insulator, located on one side of the base substrate; bit lines, arranged in the insulator, the bit lines being distributed at intervals along first direction and extending along second direction; active bodies, located in the insulator, the active bodies being located on sides of respective bit lines facing away from the base substrate, orthographic projection of each active body on the base substrate at least partially coinciding with the orthographic projection of a respective bit line on the base substrate, and the active bodies being distributed at intervals along second direction; and word lines, located in the insulator and located on sides of respective bit lines facing away from the base substrate, the word lines being distributed at intervals along second direction and extending along first direction, and only one word line being arranged between two adjacent active bodies in second direction.