Semiconductor Memory Cell with Oxide Transistors for Compact Dual-Port Access
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Solution Overview
Problem
Static random access memory (SRAM) devices, particularly dual-port SRAM, face challenges in achieving a small cell area and independent control of data write and read operations, which are essential for high-speed access in applications like image processing.
Innovation Solution
A semiconductor device configuration using first to third transistors and a capacitor, where the transistors are connected in a specific wiring arrangement to enable independent control of data write and read operations, utilizing oxide semiconductor transistors to reduce the cell area and improve switching characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dual-port SRAM is used to enable independent data write and read control, then data access speed is improved, but cell area increases to 100 F2 to 150 F2
Solution Approach 1:
The patent merges the functions of multiple transistors into a compact configuration where three transistors and one capacitor collectively perform both independent write and read operations. The first transistor controls write access to the storage node, while the second and third transistors enable read operations through a shared read line, combining multiple functions into a reduced transistor count that achieves dual-port functionality with smaller area.
2Ease of operation
If conventional SRAM configuration with six or more transistors is used, then independent data write and read control is achieved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates redundant transistors from the conventional six-transistor SRAM configuration. By removing unnecessary transistors and using the capacitor to store data directly on the storage node, the design achieves independent write and read control with only three transistors, significantly reducing device complexity while maintaining operational functionality.
Solution Approach 2:
The capacitor in the patent serves multiple functions: it stores data on the storage node, enables read operations through capacitive coupling, and works with the three-transistor configuration to provide both write and read control. This multi-functional use of the capacitor reduces the need for additional transistors that would otherwise be required for separate write and read control circuits.
Data Source
AI summary
A semiconductor device with a small cell area and excellent data read/write capability is achieved. In the semiconductor device, a wiring for writing data is provided, and a first transistor with a low off-state current is turned on to supply data to a gate of a second transistor and is turned off so that electric charge corresponding to data is retained. Moreover, a wiring for reading data is provided, and a third transistor is turned on so that data is read out in accordance with the on/off state of the second transistor retaining the electric charge. With this configuration, data write and data read are achieved in the same cycle.