Semiconductor Memory Cell Programming for Data Retention
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Solution Overview
Problem
Existing flash memory technologies face a tradeoff between data retention time and data writing time, where increasing data retention requires longer writing times, and higher voltages for faster writing can damage memory cells and widen threshold voltage distribution.
Innovation Solution
A semiconductor device and method that programs memory cells to a first level for quick writing and then to a second level for extended data retention, using a control circuit to manage the process and reduce CPU processing time, with flags to optimize programming and avoid wasteful operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a larger amount of charge is stored in the charge storage layer to secure long-term data retention, then data retention time is improved, but data writing time increases
Solution Approach 1:
The patent segments the data writing process into two distinct programming phases: a first programming process that writes initial data to the charge storage layer, and a second programming process that supplements the charge to achieve the final threshold voltage. This segmentation allows the system to optimize each phase independently, reducing the total writing time while ensuring sufficient charge storage for long-term retention.
Solution Approach 2:
The first programming process performs preliminary action by writing the initial data to the charge storage layer before the second programming process supplements the charge. This preliminary programming establishes a baseline charge level, allowing the second programming to focus only on the additional charge needed to reach the target threshold voltage, thereby reducing overall programming time.
2Loss of time
If higher voltage is applied to the memory cell to shorten data writing time, then data writing time is reduced, but memory cell damage occurs and threshold voltage distribution widens
Solution Approach 1:
The patent employs dynamic voltage adjustment by applying different voltage levels during different programming phases. The first programming process uses a first voltage level to write initial data, and the second programming process uses a second voltage level (higher than the first but not exceeding the maximum rating) to supplement the charge. This dynamic approach allows faster programming without applying excessive voltage that would damage the memory cell.
Solution Approach 2:
The patent changes the voltage parameter between programming phases: the first programming process operates at a lower voltage level, and the second programming process operates at a higher voltage level within safe limits. This parameter change enables the system to achieve faster programming speeds in the second phase without compromising memory cell integrity, as the voltage remains below the maximum rating throughout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces data writing time while ensuring sufficient data retention time, avoiding the need for higher voltages and minimizing memory cell damage, thus improving CPU efficiency and data storage reliability.
Implementation Method 1
Data can be written into the memory cell (that is, charge is stored in the charge storage layer) by injecting electrons or the like in the charge storage layer. Hot electrons thus generated between the source and drain are injected into the charge storage layer, and are accumulated therein.
Implementation Method 2
a high voltage is applied between the source and drain of the transistor that forms the memory cell, and a positive voltage is applied to the control gate thereof. Hot electrons thus generated between the source and drain are injected into the charge storage layer
Data Source
AI summary
The invention is a semiconductor device that includes a memory cell array having non-volatile memory cells, and a control circuit that writes data into the memory cell array by programming memory cells to be programmed to a first level and then programming the memory cells to a second level, and its control method. According to the present invention, the time necessary for writing data can be reduced by shortening the time for programming to the first level. Further, a required data retention time can be secured by programming to the second level.