Semiconductor Memory Cell With Integrated Resistance Elements
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Solution Overview
Problem
Current semiconductor devices face challenges in performing product-sum calculations with high power efficiency while maintaining a small memory cell area, as they require high resistance values that are difficult to achieve with MOSFETs without increasing the occupied area and manufacturing cost.
Innovation Solution
The semiconductor device incorporates a memory cell array with flip-flop circuits and resistance elements connected in specific configurations, including cross-joined inverter circuits and transfer field effect transistors, to achieve the necessary resistance values with a small area, allowing for efficient product-sum calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a MOSFET is used to achieve high resistance values for product-sum calculation, then the resistance value can be increased, but the occupied area and manufacturing cost increase significantly
Solution Approach 1:
The patent combines the SRAM cell structure with resistance elements in a unified memory cell configuration. The resistance elements are integrated directly into the SRAM cell circuit, merging the storage function and resistance function into a single structure, thereby achieving high resistance values without requiring separate, area-consuming components
Solution Approach 2:
The SRAM cell is designed to serve multiple functions: it acts as both a memory storage unit and a resistance element for product-sum calculation. By making the SRAM cell universal, the patent eliminates the need for dedicated resistance components, reducing overall area while maintaining the required resistance values for neural network computations
2Measurement precision
If a MOSFET channel is used as a resistor to achieve high resistance values, then the resistance increases, but the channel dimensions must be extremely small which increases manufacturing difficulty
Solution Approach 1:
The patent uses dedicated resistance elements with standard manufacturing processes rather than relying on precision-critical MOSFET channel dimensions. These resistance elements can be fabricated using conventional techniques, making the manufacturing process more robust and less sensitive to dimensional variations, thereby improving ease of manufacture while achieving the required resistance values
3Area of stationary object
If the memory cell area is reduced to lower manufacturing cost, then the occupied area decreases, but achieving the necessary resistance values becomes difficult
Solution Approach 1:
By merging the SRAM cell structure with integrated resistance elements, the patent achieves high resistance values within a compact area. The resistance elements are positioned within the existing SRAM cell footprint, allowing the memory cell to maintain small area while providing the necessary resistance for product-sum calculation in neural network applications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables high power efficiency in product-sum calculations while maintaining a small memory cell area, achieving resistance values of 1 MΩ or more necessary for processing multiple bits, thus addressing the limitations of existing technologies.
Implementation Method 1
two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two transfer field effect transistors and other end sides are respectively connected to a bit line and a bit line bar
Data Source
AI summary
A product-sum calculation with high power efficiency is performed while maintaining a small area of a memory cell. A semiconductor device includes a memory cell array in which a plurality of memory cells is arranged in a matrix. Then, each memory cell of the plurality of memory cells includes a flip-flop circuit including two inverter circuits in each of which a load field effect transistor and a drive field effect transistor are connected in series, input portions and output portions of the two inverter circuits being cross-joined to each other, two transfer field effect transistors each having a gate electrode connected to a word line, and a pair of first and second main electrode regions, the first main electrode regions being respectively connected to the output portions of the two inverter circuits, and two resistance elements of which one end sides are respectively connected to the second main electrode regions of the two transfer field effect transistors and other end sides are respectively connected to a bit line and a bit line bar.