Semiconductor Memory Cell with Segmented Volatile and Non-Volatile Regions

Solution Overview

Problem

Current semiconductor memory devices either operate quickly like volatile memories but lose data when power is off, or they retain data like non-volatile memories but operate slowly.

Innovation Solution

A semiconductor memory cell design that combines volatile and non-volatile features, using a substrate with specific conductivity types, buried layers, and a non-volatile memory configuration, such as a floating gate or resistance change element, to store data both quickly and retain it when power is discontinued, with data transfer occurring between volatile and non-volatile modes in a parallel, non-algorithmic process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If non-volatile memory devices are used to retain data without power, then data retention capability is improved, but operation speed deteriorates

Engineering Contradiction:

Improvedata retention capabilityVSAvoidoperation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The memory device is segmented into two distinct memory types: volatile memory for fast data storage and non-volatile memory for data retention. This segmentation allows each memory type to operate in its optimal performance regime, with the volatile memory providing rapid access speeds and the non-volatile memory ensuring data persistence without power

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent combines volatile and non-volatile memory technologies into a single integrated device. The volatile memory portion provides fast operation while the non-volatile memory portion ensures data retention, merging the advantages of both memory types to resolve the contradiction between speed and reliability

Inventive Principle:

Principle #5Merging (Combining)

2Speed

If volatile memory devices are used for fast operation, then operation speed is improved, but data retention capability deteriorates

Engineering Contradiction:

Improveoperation speedVSAvoiddata retention capability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The memory device is segmented into two distinct memory types: volatile memory for fast data storage and non-volatile memory for data retention. This segmentation allows each memory type to operate in its optimal performance regime, with the volatile memory providing rapid access speeds and the non-volatile memory ensuring data persistence without power

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent combines volatile and non-volatile memory technologies into a single integrated device. The volatile memory portion provides fast operation while the non-volatile memory portion ensures data retention, merging the advantages of both memory types to resolve the contradiction between speed and reliability

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If a universal memory device combines both volatile and non-volatile features, then versatility is improved, but device complexity increases

Engineering Contradiction:

Improvememory functionality versatilityVSAvoiddevice structure complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory device is segmented into two distinct memory types: volatile memory for fast data storage and non-volatile memory for data retention. This segmentation allows each memory type to operate in its optimal performance regime, with the volatile memory providing rapid access speeds and the non-volatile memory ensuring data persistence without power

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent combines volatile and non-volatile memory technologies into a single integrated device. The volatile memory portion provides fast operation while the non-volatile memory portion ensures data retention, merging the advantages of both memory types to resolve the contradiction between speed and reliability

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUSRE47381E1Forming semiconductor cells with regions of varying conductivity

Publication Date: 2019.05.07 ZENO SEMICONDUCTOR INC

AI summary

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body regionand having the first conductivity type; and a gate positioned between the first and second regions and above the top surface; wherein a state of the body region is maintained by applying a voltage to the substrate and a nonvolatile memory configured to store data upon transfer from the body region.