Semiconductor Memory Cell Voltage Control via Segmented Transistors
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Solution Overview
Problem
Current semiconductor devices face challenges in maintaining low voltage across transistors to ensure high reliability and multilevel data retention, particularly in memory cells where the voltage between the source and drain of transistors can exceed predetermined limits, leading to potential breakdown and data loss.
Innovation Solution
A semiconductor device configuration that includes a memory cell with a Si transistor and an OS transistor, where the voltage between the source and drain of the Si transistor is kept lower than a predetermined value by controlling the potential difference between the wiring and the transistor, using a specific step-by-step process for data writing and reading that involves precharging, discharging, and adjusting potentials to maintain the voltage within safe limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage between source and drain of the Si transistor is increased to improve data retention capability, then the ability to retain multilevel data is improved, but the reliability deteriorates due to potential breakdown exceeding predetermined voltage limits
Solution Approach 1:
The memory cell is divided into two separate transistors: a Si transistor for high-speed read/write operations and an OS transistor for data retention. This segmentation allows each transistor to be optimized for its specific function without compromising the other, enabling multilevel data retention while maintaining low voltage across the Si transistor to prevent breakdown.
Solution Approach 2:
The OS transistor acts as an intermediary element that assumes the burden of voltage stress and data retention responsibilities. By placing the OS transistor in series with the Si transistor in the data retention path, it mediates the voltage requirements, allowing the Si transistor to operate at safe voltage levels while the OS transistor handles the higher voltages needed for multilevel data storage.
2Reliability
If the voltage across the Si transistor is kept low to prevent breakdown and ensure reliability, then transistor reliability is improved, but the data retention capability may be insufficient for multilevel data
Solution Approach 1:
The patent merges the functionality of two different transistor types (Si and OS) into a single memory cell circuit. The Si transistor provides high-speed operation and low off-state current, while the OS transistor provides excellent data retention characteristics. This combination enables the memory cell to retain multilevel data reliably without requiring high voltage across the Si transistor.
Solution Approach 2:
The invention changes the material parameter of the transistor used for data retention from silicon-based to oxide semiconductor. This parameter change fundamentally alters the electrical characteristics, providing a transistor with extremely low off-state current that can maintain multilevel data at low voltages, thus solving the contradiction between low voltage operation and data retention capability.
3Ease of manufacture
If a single transistor structure is used to simplify device complexity, then ease of manufacture is improved, but the ability to control voltage and retain multilevel data deteriorates
Solution Approach 1:
The memory cell is segmented into two distinct transistor structures with different materials and optimization goals. The Si transistor is optimized for speed and low power during access operations, while the OS transistor is optimized for data retention. This segmentation provides the voltage control capability needed for multilevel data retention while maintaining manufacturability through standardized fabrication processes for both transistor types.
Data Source
AI summary
A highly reliable semiconductor device. In a configuration where a precharged source line is discharged to a bit line by establishing electrical continuity between the source line and the bit line through a transistor to read a potential retained at a gate of the transistor, the potential of the bit line is switched in accordance with a change in potential of the source line due to the discharge. With this configuration, the voltage between the source and drain of the transistor can be kept lower than a predetermined voltage by discharge. Accordingly, the source-drain voltage of the transistor can be kept lower than its breakdown voltage, so that the semiconductor device can have high reliability.