Semiconductor Memory Charge Segmentation for Parasitic Energy Loss
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Solution Overview
Problem
Existing semiconductor memory systems, particularly analog memories, face significant energy wastage due to parasitic capacitance in wiring, leading to inefficient energy consumption during operation.
Innovation Solution
A semiconductor device with a memory unit that includes a transfer unit connected to multiple pairs of gate and accumulation units, allowing for efficient charge transfer and accumulation, thereby reducing energy wastage by minimizing unnecessary charging and discharging of parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional memory structures are used, then charge storage function is achieved, but energy wastage occurs due to parasitic capacitance in wiring
Solution Approach 1:
The memory unit is segmented into multiple accumulation units (first, second, third accumulation units) with dedicated transfer units and gate units for each. This segmentation allows selective charging and discharging of individual accumulation units, minimizing parasitic capacitance effects in wiring by isolating charge operations to specific segments rather than affecting the entire memory structure simultaneously.
Solution Approach 2:
The patent implements dynamic control through gate units that can selectively connect or disconnect accumulation units from transfer units based on operational needs. The gate units enable the system to dynamically adjust which accumulation units are active, allowing charge to be stored in only the necessary units during different operational phases, thereby reducing energy wastage from charging/discharging unnecessary parasitic capacitances.
2Productivity
If multiple accumulation units are used, then charge handling efficiency is improved, but device complexity increases
Solution Approach 1:
Each accumulation unit is designed with identical structural components (transfer unit, gate unit, accumulation unit configuration), making them universally interchangeable in terms of function and design. This universality allows the system to handle multiple charges efficiently through parallel operation of identical modules, improving productivity while controlling complexity through standardized design patterns that can be replicated.
Solution Approach 2:
The memory unit employs a nested hierarchical structure where transfer units and gate units are organized in a systematic pattern around multiple accumulation units. The first transfer unit connects to both first and second accumulation units, while the second transfer unit connects to second and third accumulation units, creating an overlapping nested arrangement that improves charge handling efficiency through shared pathways while managing complexity through structured organization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively suppresses energy wastage by directly storing analog signals in the memory unit, reducing energy consumption associated with parasitic capacitances, and optimizing charge handling processes.
Implementation Method 1
the gate unit selects the accumulation unit that accumulates a charge
Implementation Method 2
the transfer unit transfers a charge from the input unit to the accumulation unit selected by the gate unit
Implementation Method 3
the accumulation unit accumulates a charge transferred from the transfer unit
Implementation Method 4
the transfer unit transfers a charge accumulated in the accumulation unit selected by the gate unit, to the output unit
Data Source
AI summary
The present disclosure relates to a semiconductor device enabling to suppress waste of energy consumption. There is provided a semiconductor device including: an input unit configured to input a charge; a memory unit configured to collect and accumulate a charge from the input unit; and an output unit configured to detect and output a charge accumulated in the memory unit. The memory unit includes a transfer unit to which a plurality of pairs of a gate unit and an accumulation unit is connected, the gate unit selects the accumulation unit that accumulates a charge, the transfer unit transfers a charge from the input unit to the accumulation unit selected by the gate unit, the accumulation unit accumulates a charge transferred from the transfer unit, and the transfer unit transfers a charge accumulated in the accumulation unit selected by the gate unit, to the output unit. The present disclosure can be applied to, for example, an analog memory device.