Semiconductor Memory Clock Phase Alignment Training
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Solution Overview
Problem
Conventional clock alignment training operations in semiconductor devices, particularly under auto-synchronous mode, face issues with phase misalignment and jitter, leading to ineffective data input/output operations.
Innovation Solution
A semiconductor memory device with a system clock input block, data clock input block, phase detection blocks, and a clock select block that compare and synchronize the phases of system and data clocks, determining a reverse control signal and clock select signal to correct phase differences and align clocks within a preset error range, even in the presence of jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If auto-synchronous mode is used for clock alignment training, then the phase difference between system clock and data clock can be controlled to fall within a predetermined range, but phase misalignment and jitter occur leading to ineffective data input/output operations
Solution Approach 1:
The clock alignment training operation is divided into two distinct phases: a coarse adjustment phase that brings the phase difference within a predetermined range, and a fine adjustment phase that precisely synchronizes the phases. This segmentation allows each phase to optimize for its specific function, preventing the phase misalignment and jitter issues that occur when using auto-synchronous mode alone.
Solution Approach 2:
The patent performs preliminary coarse adjustment of the data clock phase before the final fine adjustment. By first establishing a rough phase alignment within a predetermined range, the system prepares the clock signals for subsequent precise synchronization, ensuring that the fine adjustment phase operates from a stable baseline and avoids phase misalignment issues.
2Measurement precision
If normal training mode is used for precise phase synchronization, then phase alignment precision is improved, but the complexity of the training operation increases
Solution Approach 1:
The training operation is segmented into coarse adjustment and fine adjustment phases. The coarse adjustment phase uses simpler comparison logic to determine when the phase difference is within the predetermined range, while the fine adjustment phase implements the more complex precise synchronization only when necessary. This segmentation reduces overall complexity compared to always executing normal training mode.
Solution Approach 2:
The patent applies partial action by implementing normal training mode (precise phase synchronization) only when the coarse adjustment phase indicates that the phase difference exceeds the predetermined range. When the phases are already sufficiently aligned, the system skips the complex fine adjustment phase, reducing operational complexity while maintaining precision when needed.
3Speed
If data clock frequency is doubled to achieve high speed data input/output, then data transfer speed is improved, but phase alignment between system clock and data clock becomes more difficult to maintain
Solution Approach 1:
The patent performs preliminary phase alignment adjustment before the high speed data input/output operations begin. By establishing precise phase synchronization during the training phase, the system prepares the clock signals to maintain alignment even when the data clock frequency is doubled, preventing phase misalignment during high speed operation.
Solution Approach 2:
The patent implements a feedback mechanism during clock alignment training where the phase detector continuously monitors the phase difference between system clock and data clock, and the control logic adjusts the data clock phase based on this feedback. This feedback loop ensures that phase alignment is dynamically maintained even when the data clock frequency is doubled for high speed operation.
Data Source
AI summary
A semiconductor memory device includes a system clock input block configured to be inputted with a system clock, a data clock input block configured to be inputted with a data clock, a first phase detection block configured to compare a phase of the system clock, generate a first phase detection signal, and determine a logic level of a reverse control signal in response to the first phase detection signal, a second phase detection block configured to compare a phase of a clock acquired by delaying the system clock by a correction time, generate a second phase detection signal, and determine a logic level of a clock select signal in response to the first and second phase detection signals, and a clock select block configured to select and output the data clock or a clock acquired by delaying the data clock.