Semiconductor Memory Device Column Power Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing power dissipation during operation and standby while maintaining high memory capacity, particularly in single port SRAMs where controlling the potential of source lines for each column is necessary without increasing memory cell size.
Innovation Solution
The semiconductor memory device incorporates a second power supply line that crosses the substrate region of each memory cell, allowing for individual voltage control of the low side source line, reducing power consumption by short-circuiting the source nodes of driver transistors and minimizing potential differences, thereby enhancing operational stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory capacity is increased by arranging memory cells with high density, then the memory capacity is improved, but the power dissipation increases
Solution Approach 1:
The semiconductor substrate is divided into multiple independent column regions, each with its own power supply line. This segmentation allows individual control of power supply voltage for each column, enabling selective activation of memory cell columns to reduce overall power dissipation while maintaining high memory capacity through dense cell arrangement.
Solution Approach 2:
The power supply voltage to memory cell columns is made dynamically controllable, allowing the system to adjust which columns are active based on access patterns. This dynamic control reduces power dissipation by keeping inactive columns in a low-power state while maintaining the ability to quickly activate any column when needed, thus supporting high memory capacity without proportional power increase.
2Loss of energy
If the source line potential is controlled for each column to reduce power dissipation, then the power dissipation is reduced, but the device complexity increases
Solution Approach 1:
The power supply system is segmented into multiple independent lines, each serving a specific column region. This segmentation enables granular control of power supply voltage at the column level, reducing power dissipation by selectively powering only active columns while avoiding the need for complex per-cell control mechanisms.
Solution Approach 2:
The segmented power supply lines serve multiple functions: they provide power to memory cell columns, enable independent column selection, and facilitate power management. This multi-functionality reduces the need for additional dedicated control circuits, thereby reducing device complexity while achieving power dissipation reduction through column-level potential control.
3Ease of manufacture
If the well regions are arranged linearly to simplify interconnection layout, then the ease of manufacture is improved, but the area of memory cells increases
Solution Approach 1:
The linear arrangement of well regions is segmented into column-specific groups, each associated with a particular power supply line. This segmentation maintains the manufacturing simplicity of linear layouts while reducing the effective area required per memory cell by enabling selective activation of column regions, thus keeping inactive regions in a low-power state without requiring physical removal.
Data Source
AI summary
Source contacts of driver transistors are short-circuited through the use of an internal metal line within a memory cell. This metal line is isolated from memory cells in an adjacent column and extends in a zigzag form in a direction of the columns of memory cells. Individual lines for transmitting the source voltage of driver transistors can be provided for each column, and the source voltage of driver transistors can be adjusted also in units of memory cell columns in the structure of single port memory cell.