Semiconductor Memory Common Pin Address Data Mask Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices require a large-sized circuit to process address and data mask information separately, leading to increased chip size and current consumption.
Innovation Solution
A semiconductor memory device that processes address and data mask information using a common pin, employing a buffer unit, shift register unit, and driving unit to align and output information sequentially, eliminating the need for separate circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuits are used to process address and data mask information, then processing reliability is improved, but chip size increases
Solution Approach 1:
The patent combines the address processing circuit and data mask processing circuit into a single integrated circuit that receives both address and data mask information through a common pin. The circuit uses a single buffer unit, shift register unit, and driving unit to process both types of information sequentially, eliminating the need for separate circuits while maintaining processing reliability through proper timing control and signal separation logic.
Solution Approach 2:
The patent designs a multi-functional circuit that can process both address information and data mask information through the same pin and processing units. The buffer unit, shift register unit, and driving unit are configured to handle different types of information (address or data mask) based on control signals, making the circuit universal and eliminating the need for dedicated separate circuits for each function.
2Measurement precision
If separate circuits are used to process address and data mask information, then processing accuracy is improved, but current consumption increases
Solution Approach 1:
The patent merges the address processing and data mask processing into a single circuit that operates sequentially rather than in parallel. By using one set of processing units (buffer, shift register, driving unit) for both functions instead of two separate circuits, the total current consumption is reduced while processing accuracy is maintained through proper timing control and signal validation logic.
Solution Approach 2:
The patent employs periodic action by sequentially processing address information and data mask information through the same circuit units at different time periods. The circuit alternates between handling address signals and data mask signals based on control logic, ensuring that each type of information is processed with the required accuracy while avoiding the continuous power consumption of parallel separate circuits.
3Quantity of substance
If a common pin is used for address and data mask information, then pin count is reduced, but signal interference increases
Solution Approach 1:
The patent applies preliminary action by using control logic that determines in advance whether the incoming signal on the common pin is address information or data mask information. Based on this preliminary identification, the circuit configures its processing path accordingly, separating the signals before they can interfere with each other, thus reducing signal interference while utilizing the common pin effectively.
Solution Approach 2:
The patent introduces an intermediary control mechanism that mediates between the common pin and the processing circuits. This intermediary logic identifies the type of information being transmitted and routes it to the appropriate processing path, preventing direct interference between address and data mask signals while allowing both to share the common pin.
Data Source
AI summary
A semiconductor memory device is capable of controlling an address and data mask information through the use of a common part, thereby reducing chip size. The semiconductor memory device for receiving the addresses and data mask information via a common pin includes a buffer unit and a shift register unit. The buffer unit receives the addresses and data mask information. The shift register unit is comprised of a plurality of latch stages connected in series, for sequentially latching the addresses and data mask information being inputted in series, and an address output unit and a data mask information output unit for outputting information from different latch stages.