Semiconductor Memory Device Concurrent Access Repair Determination
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Solution Overview
Problem
In semiconductor memory devices, the determination of defective addresses by repair determining circuits takes a long time, leading to delayed random RAS access and limited parallel operations, which can be improved by concurrent access to normal and redundant memory cells.
Innovation Solution
A semiconductor memory device with a first circuit accessing normal memory cells and a second circuit accessing redundant memory cells from a different memory mat, allowing parallel execution of access operations and determination, thereby shortening the tRCD period and improving access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the repair determining circuit determines whether an address is defective before accessing memory cells, then defective addresses can be identified and redundant memory cells can be accessed, but the determination process takes a long time and delays random RAS access
Solution Approach 1:
The patent applies preliminary action by pre-organizing redundant memory cells and their associated decoding circuits before actual memory access operations. The redundant memory cell array is prepared in advance with dedicated row decoders and sub-word line drivers, so that when a defective address is detected, the system can immediately switch to the pre-prepared redundant path without time-consuming reconfiguration.
Solution Approach 2:
The patent implements dynamics by making the memory access path selectable and changeable. The system dynamically switches between normal memory cell access and redundant memory cell access based on real-time defect detection. The row decoder and sub-word line drivers are designed to be controllable, allowing the system to adaptively route access operations to either normal or redundant memory cells depending on the detected address status.
2Reliability
If the determination operation by the repair determining circuit is completed before the sub-word line is activated, then defective addresses can be accurately identified, but parallel operations are limited and access speed is reduced
Solution Approach 1:
The patent applies preliminary action by pre-positioning redundant memory cells and their decoding infrastructure before access operations begin. The redundant memory cell array, row decoders, and sub-word line drivers are all prepared in advance, enabling the system to perform determination and access operations in parallel without compromising detection accuracy.
Solution Approach 2:
The patent applies dimensionality change by adding a redundant memory cell array as a parallel dimension to the normal memory cell array. This creates two independent access paths that can operate simultaneously - one for normal cells and one for redundant cells. The system can initiate access to both paths at the same time, with the defective address detection running concurrently, thereby breaking the sequential dependency and improving productivity.
3Reliability
If redundant memory cells are prepared to replace defective normal memory cells, then memory device reliability is improved, but the device complexity increases due to additional circuits and memory cells
Solution Approach 1:
The patent applies segmentation by dividing the memory device into distinct segments: normal memory cell arrays and redundant memory cell arrays. Each segment has its own dedicated row decoders and sub-word line drivers. This segmentation allows the redundant portion to be independently controlled and activated only when needed, managing complexity through modular organization rather than integrating all functions into a single complex structure.
Solution Approach 2:
The patent applies universality by designing the redundant memory cell array and its associated decoding circuits to serve multiple purposes. The same row decoder structure and sub-word line driver architecture used for normal memory cells are also used for redundant memory cells, allowing these components to function universally for both normal and redundant access operations. This reduces overall complexity by reusing proven designs rather than creating entirely new circuits.
Data Source
AI summary
There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.