Semiconductor Memory Device Concurrent Test Data Write Read
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Solution Overview
Problem
Conventional semiconductor memory devices cannot perform data write and read operations simultaneously due to the shared use of I/O pins, leading to increased testing times and manufacturing costs as the integration density of these devices increases, necessitating a method for simultaneous input and output of test data during testing.
Innovation Solution
A semiconductor memory device with a memory cell array and address/data handling components that allow simultaneous access to multiple memory banks during testing, using address pins for inputting row and column addresses and data pins for inputting/write and outputting read data, respectively, enabling concurrent data write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the same I/O pins are used for both data input and output operations, then the device complexity is reduced, but the testing time increases because simultaneous data write and read operations cannot be performed
Solution Approach 1:
The memory device is divided into multiple independent memory banks (first memory bank and second memory bank). Each bank can be independently accessed for read or write operations, allowing parallel processing. The controller segments the testing process into simultaneous write operations on one bank and read operations on another bank, thereby reducing testing time without increasing device complexity.
2Device complexity
If conventional sequential testing methods are used where all test data is input first and then output is received, then the device structure remains simple, but the productivity decreases due to increased testing time
Solution Approach 1:
The testing process is made continuous by allowing write operations and read operations to occur simultaneously in different memory banks. While the controller writes test data to the first memory bank, it concurrently reads data from the second memory bank. This eliminates the idle time between writing all test data and then reading it, maintaining continuous useful action and improving productivity.
3Manufacturing precision
If the line width of the semiconductor chip is reduced to increase integration density, then the manufacturing precision improves, but the probability of manufacturing defects increases leading to more extensive testing
Solution Approach 1:
The memory device is divided into multiple independent memory banks that can be tested in parallel. This segmentation allows comprehensive testing of multiple banks simultaneously, increasing the detection capability for manufacturing defects. By testing multiple banks concurrently rather than sequentially, the system can identify defects more efficiently despite the increased defect probability from reduced line width.
4Loss of time
If parallel bit test is used to test multiple devices simultaneously through representative data I/O pads, then the testing time for multiple devices is reduced, but the testing completeness decreases because not all data I/O pads are used
Solution Approach 1:
The memory device is segmented into multiple banks that can be independently accessed. This allows the system to perform comprehensive testing of all data I/O pads by directing test operations to different banks, rather than using only representative pads. The segmentation enables full coverage testing while maintaining efficient parallel operation across multiple banks.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory banks, an address input portion which receives a row address and a column address through address pins during a normal mode operation and which receives the row address, the column address and write data through the address pins during a test mode operation, an address decoder which accesses one of the plurality of memory banks during the normal mode operation and at least two of the plurality of memory banks during the test mode operation in response to the row address and the column address, a data input portion which inputs write data applied through data pins to the memory cell array during the normal mode operation and which inputs write data output from the address input portion to the memory cell array during the test mode operation, and a data output portion which outputs read data output from the memory cell array to the data pins during the normal mode operation and the test mode operation.