3D Stacked Semiconductor Memory Device Contact Area Reduction
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Solution Overview
Problem
In nonvolatile semiconductor memory devices with a three-dimensional stacked structure, the increasing number of stacked layers leads to a larger chip area due to increased contact regions for connecting bit lines and word lines with circuit transistors, hindering the achievement of lower costs and higher density.
Innovation Solution
The semiconductor memory device features a configuration where the number of first lines and contacts in upper cell array layers is reduced compared to lower layers, with contacts extending through the dividing space between lines in lower layers to connect with diffusion regions on the substrate, thereby minimizing the contact arrangement area and chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked cell array layers is increased to achieve higher memory capacity, then the memory capacity is improved, but the chip area increases due to increased contact regions
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked structure. Multiple cell array layers are stacked vertically, allowing memory capacity to increase without proportionally increasing chip area. The contact regions are arranged in the vertical dimension rather than spreading out horizontally, resolving the contradiction between capacity and area.
Solution Approach 2:
The patent implements a nested structure where multiple cell array layers are stacked one on top of another. Each layer contains memory cells formed at intersections of bit lines and word lines, with contact regions nested vertically. This nesting allows higher integration density while controlling the horizontal chip area.
2Productivity
If the number of stacked layers is increased to achieve higher density, then the memory capacity is improved, but the contact arrangement area increases preventing lower costs
Solution Approach 1:
The patent moves the contact arrangement from a horizontal plane to a vertical stack. Contact regions for multiple bit lines are arranged in the vertical dimension across different cell array layers, rather than spreading horizontally. This dimensional change increases memory density while keeping the contact arrangement area compact and cost-effective.
3Reliability
If more contacts are provided to connect all bit lines in stacked layers, then the connectivity is improved, but the chip area and manufacturing complexity increase
Solution Approach 1:
The patent implements a universal contact structure where a single contact region in a lower cell array layer serves multiple bit lines from different stacked layers. The contact connects to bit lines BL1 and BL2 simultaneously, reducing the total number of contacts needed while maintaining full connectivity. This multi-functionality reduces manufacturing complexity and chip area.
Data Source
AI summary
A semiconductor memory device comprises a semiconductor substrate; a memory block formed on the semiconductor substrate and including plural stacked cell array layers of cell arrays each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contacts extending in the stack direction of the cell array layers and connecting the first lines in the cell arrays with diffusion regions formed on the semiconductor substrate. A certain one of the cell array layers is smaller in the number of the first lines divided and the number of contacts connected than the cell array layers in a lower layer located closer to the semiconductor substrate than the certain one.