3D Semiconductor Memory Contact via Sidewall Capping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor memory devices is to enhance the integration density while maintaining efficient electrical contact and reducing resistance, particularly in 3-dimensional structures where physical limitations restrict the size of memory cells.
Innovation Solution
A semiconductor memory device with a stacked structure featuring alternately stacked conductive and interlayer insulating patterns, including a through-hole with a channel pattern and capping conductive patterns that increase the contact area and reduce resistance by forming a second capping conductive pattern on the sidewall of the first capping conductive pattern, along with a contact plug.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a 3-dimensional structure to increase integration density, then the integration density is improved, but the electrical contact area and resistance become problematic
Solution Approach 1:
The patent transitions from a planar contact structure to a three-dimensional contact structure by forming a contact pattern that extends vertically along the sidewall of the gate capping pattern. This dimensional change increases the contact area without increasing the planar footprint, thereby improving electrical contact quality while maintaining high integration density in the 3D memory structure.
Solution Approach 2:
The contact pattern is formed within the confines of the gate capping pattern's sidewall, creating a nested structure where the contact pattern is embedded along the vertical surface. This nesting approach allows the contact structure to utilize the vertical space already defined by the gate structure, maximizing contact area without compromising the overall device layout or integration density.
2Reliability
If the contact area is increased to reduce resistance, then the electrical contact quality is improved, but the device area and complexity increase
Solution Approach 1:
The contact structure is segmented into two distinct parts: a first capping pattern forming the top surface of the gate structure, and a contact pattern formed separately along the sidewall of the first capping pattern. This segmentation allows each component to be optimized independently - the first capping pattern for gate functionality and the contact pattern for electrical contact - thereby reducing overall device complexity while improving contact quality.
Solution Approach 2:
The contact pattern is localized specifically to the sidewall region of the gate capping pattern, concentrating the electrical contact function in a specific location rather than distributing it across the entire device area. This local quality approach increases contact area where needed without unnecessarily increasing overall device complexity or area.
Data Source
AI summary
The semiconductor memory device includes a stacked structure including conductive patterns and interlayer insulating patterns which are alternately stacked, a through-hole configured to pass through the stacked structure; a channel pattern formed inside the through-hole, a first capping conductive pattern formed on the channel pattern, a second capping conductive pattern formed on a sidewall of the first capping conductive pattern and surrounding the first capping conductive pattern, and a contact plug formed on the first capping conductive pattern and the second capping conductive pattern.