Semiconductor Memory Device Cross-Point Wiring Structure

The patent introduces a third dimension by stacking memory cells vertically to form a three-dimensional cross-point structure. Multiple electrodes are arranged in different vertical layers rather than being planarly distributed, which enables multiple filament paths through vertical stacking instead of horizontal wiring expansion. This dimensional transition reduces wiring complexity while maintaining multi-valued storage capability.

The patent implements nested wiring structures where local bit lines and local word lines are positioned within memory blocks, while global bit lines and global word lines extend outside the memory blocks. This nested arrangement allows hierarchical signal distribution and reduces the number of external connections required, thereby simplifying wiring line connections while supporting multi-valued cell operations.

The patent transitions from two-dimensional planar wiring to three-dimensional stacked wiring by forming multiple electrode layers vertically. This allows multiple filament paths to be established through vertical stacking of memory cells rather than horizontal expansion of wiring lines, thereby increasing storage capacity per cell without proportionally increasing the physical area occupied by wiring infrastructure.

The patent merges multiple wiring functions into shared global bit lines and global word lines that serve multiple memory blocks. By combining local and global wiring layers and utilizing common signal paths across stacked cells, the design reduces redundant wiring and minimizes the total physical area required for interconnect structures while maintaining high storage capacity.