3D Semiconductor Memory Integration Density via Solid Phase Crystallization
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the cost of advanced equipment and difficulties in fabrication processes, making three-dimensional semiconductor memory devices expensive and unreliable compared to two-dimensional devices.
Innovation Solution
The semiconductor devices feature gate and insulation patterns alternately stacked on a substrate with a through region, including channel structures with different semiconductor regions and grain sizes, and a data storage layer, fabricated using heat treatment processes to enhance pattern fineness and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional semiconductor memory devices are produced to increase integration density, then integration density is improved, but manufacturing cost increases and reliability concerns arise
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked along the vertical direction, with each layer containing channel structures, gate electrodes, and insulation patterns. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate rather than only the horizontal plane.
Solution Approach 2:
The three-dimensional memory structure is divided into multiple discrete memory cell layers stacked vertically. Each layer is further segmented into channel structures with specific grain sizes, and gate electrodes are divided into word line gates and selection gates. This segmentation allows for modular fabrication and improves overall device reliability by isolating potential failure points within individual layers.
2Manufacturing precision
If advanced pattern forming technology is used to increase integration density, then pattern fineness is improved, but manufacturing cost increases due to expensive equipment
Solution Approach 1:
The patent employs solid phase crystallization heat treatment to transform the grain structure of semiconductor regions in situ. By controlling temperature parameters during heat treatment, the grain size of semiconductor regions can be precisely adjusted to optimize electrical characteristics. This parameter-based control achieves fine pattern definition without requiring expensive advanced lithography equipment.
Solution Approach 2:
The patent replaces mechanical/chemical lithography processes with thermal field-based solid phase crystallization. Instead of using complex photoresist patterning and etching sequences that require expensive equipment, the invention uses controlled heat treatment to define and refine patterns through phase transformation, simplifying the manufacturing process and reducing equipment costs.
3Productivity
If three-dimensional semiconductor memory devices are produced to increase integration density, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary solid phase crystallization heat treatment on semiconductor regions before subsequent fabrication steps. By pre-forming the grain structure and electrical characteristics of channel structures early in the process, later fabrication steps are simplified. This preliminary action reduces overall process complexity despite the three-dimensional architecture.
Solution Approach 2:
The heat treatment process serves multiple functions: it defines grain boundaries, establishes electrical characteristics, and refines pattern geometry. This multi-functional approach consolidates several potential process steps into one, reducing fabrication complexity while achieving the desired three-dimensional memory structure with controlled electrical properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases integration density and reduces costs by improving pattern fineness and reliability of three-dimensional semiconductor memory devices, achieving higher performance and efficiency.
Implementation Method 1
a first heat treatment process to form the first semiconductor layer; forming a second heat treatment process to form the second semiconductor layer
Data Source
AI summary
Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.