Semiconductor Memory Data Line Reduction via Single-Phase Transmission
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Solution Overview
Problem
Current dynamic random access memory (DRAM) technologies face challenges in reducing the number of data lines, leading to high power consumption, heat dissipation issues, and complex routing complexities, which affect performance.
Innovation Solution
The semiconductor integrated circuit employs a single-phase transmission manner, reducing the number of data lines by using a reference data line and a local read-write conversion module with distinct discharge speeds to enhance read performance, and incorporates an amplifier module to amplify data signals based on a reference signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-phase transmission is used with complementary data lines, then data transmission reliability is improved, but the number of data lines increases leading to higher power consumption and heat dissipation
Solution Approach 1:
The patent extracts only one phase of the dual-phase transmission signal, eliminating the need for complementary data lines. By using a single data line instead of two complementary lines, the power consumption and heat dissipation are reduced while maintaining data transmission functionality through single-phase transmission with reference voltage levels.
Solution Approach 2:
The patent merges the functions of multiple data lines into a single data line by using different voltage levels (first voltage level for logic 1, second voltage level for logic 0) to represent binary states. This consolidation reduces the number of physical lines needed while preserving data transmission reliability.
2Reliability
If dual-phase transmission is used with complementary data lines, then data transmission reliability is improved, but routing complexity increases
Solution Approach 1:
The patent removes one phase from the dual-phase transmission system, extracting only the necessary single-phase signal path. This elimination of redundant complementary lines directly reduces routing complexity while maintaining sufficient reliability through proper voltage level management and sensing mechanisms.
3Ease of manufacture
If reference module discharges at the same speed as local read-write conversion module, then discharge control is simplified, but read performance deteriorates due to inconsistent sense margins
Solution Approach 1:
The patent applies different discharge characteristics to different modules: the reference module discharges at a slower rate while the local read-write conversion module discharges at a faster rate. This local differentiation in discharge speeds ensures that sense margins remain consistent for both logic 0 and logic 1 readings, improving read performance while maintaining manageable discharge control through dedicated control circuits.
4Productivity
If multiple data lines are used, then data transmission capacity is improved, but heat dissipation increases
Solution Approach 1:
The patent combines multiple data line functions into a single data line by utilizing different voltage levels to represent different logic states. This merging approach maintains data transmission capacity while reducing the number of active lines, thereby decreasing overall heat dissipation in the system.
Data Source
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AI summary
Embodiments of the present invention provide a semiconductor integrated circuit and a memory, and relates to the field of semiconductor technologies. The semiconductor integrated circuit includes a first data line connected to a bit line (BL) through a column selection module (10) and a first complementary data line connected to a complementary bit line through the column selection module (10), a second data line, and a reference data line. The reference data line is configured to provide a reference signal. The semiconductor integrated circuit further includes a local read-write conversion module (11) configured to perform, in response to a read-write control signal, data transmission between the first data line and the second data line and data transmission between the first complementary data line and the second data line during a read-write operation; and an amplifier module (13) configured to receive a data signal of the second data line and the reference signal and amplify the data signal of the second data line. The reference signal serves as a reference for amplifying the data signal of the second data line.