Semiconductor Memory Dual-Row Decoder RC Delay Reduction
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high-speed operations while maintaining a compact circuit area, particularly in three-dimensionally stacked memory cells where RC delays and voltage application timing affect read and write operations.
Innovation Solution
The semiconductor memory device employs a dual-row decoder module configuration, where lower word lines are driven from one side and upper word lines are driven from both sides, optimizing voltage application timing and reducing RC delays, and adjusts ramp rates for non-selected word lines to improve data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If word lines are driven from both sides to reduce RC delays, then operation speed is improved, but circuit area increases
Solution Approach 1:
The memory device is divided into a first memory device and a second memory device, each handling different sets of word lines. The first row decoder module drives first word lines from one side, while the second row decoder module drives second word lines from both sides. This segmentation allows different driving strategies to be applied to different regions, optimizing speed where needed while controlling overall circuit area.
Solution Approach 2:
Different word line driving strategies are applied to different regions of the memory device. Specifically, second word lines that benefit most from reduced RC delays are driven from both sides, while first word lines are driven from one side. This local optimization approach ensures that the circuit area increase is minimized while still achieving speed improvement in the most critical paths.
2Reliability
If voltage is applied to non-selected word lines to prevent data disturbance, then data reliability is improved, but operation time increases
Solution Approach 1:
The patent applies voltage to non-selected word lines in advance of the main read or write operation. By pre-charging or pre-discharging these word lines to appropriate voltage levels, the system prevents data disturbance in neighboring memory cells before the actual operation occurs, thereby improving data reliability without significantly extending the critical operation time.
Solution Approach 2:
The voltage application to non-selected word lines is performed periodically at specific phases of the memory operation cycle. This timing strategy ensures that the protective voltage is applied when most needed to prevent data disturbance, while minimizing the overall time impact on read and write operations.
Data Source
AI summary
A semiconductor memory device includes first and second memory cells, first and second word lines that are connected to the first and second memory cells, respectively, a first transistor connected to one end of the first word line, and second and third transistors respectively connected to first and second ends of the second word line. During a read operation on the first and second memory cells, when the first word line is selected, a first voltage is applied to the second word line, and then a second voltage is applied to the first word line, and when the second word line is selected, the first voltage is applied to the first word line, and then the second voltage is applied to the second word line. The second voltage is applied to the first word line for a longer duration than is applied to the second word line.