Semiconductor Memory Power Decoupling Capacitor Layout
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Solution Overview
Problem
In semiconductor memory devices, the formation of high-capacitance decoupling capacitors in peripheral circuit regions is hindered by high resistance in buried contacts, making it difficult to implement single stage cell type decoupling capacitors due to manufacturing process limitations.
Innovation Solution
A semiconductor memory device design where a plurality of capacitors are formed in the peripheral circuit region with a bottom conductive layer connecting them in parallel, and a self-align contact layer in the cell array region, eliminating the need for a buffer layer and allowing direct connection to the metal interconnection, thus reducing resistance and enabling both single and two stage cell type decoupling capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a decoupling capacitor is formed in the peripheral circuit region using the same structure as the cell capacitor, then the capacitance value increases, but the resistance of the connection line increases due to the buried contact structure
Solution Approach 1:
The patent transitions from a two-dimensional planar connection structure to a three-dimensional stacked structure by introducing multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) at different vertical levels. This dimensional change allows the connection line to bypass the high-resistance buried contact and achieve lower resistance through alternative conduction paths in the vertical dimension.
2Ease of manufacture
If a buffer layer is used to connect the storage electrode to the buried contact, then the manufacturing process is simplified, but the resistance increases and single stage cell type decoupling capacitors cannot be implemented
Solution Approach 1:
The patent extracts and removes the buffer layer from the connection structure. By eliminating this intermediate layer, the design achieves direct connection between the storage electrode and the conductive layers, thereby reducing the number of interfaces and minimizing resistance while still maintaining manufacturing feasibility through the alternative conductive layer paths.
3Reliability
If the decoupling capacitor is directly connected to the metal interconnection without a buffer layer, then the resistance decreases, but manufacturing process limitations prevent implementation of single stage cell type
Solution Approach 1:
The patent performs preliminary actions by pre-forming the first, second, and third conductive layers during the manufacturing process before final interconnection. The third conductive layer is specifically prepared in advance to enable direct connection to the metal interconnection, and the self-align contact layer is pre-positioned to facilitate subsequent single stage cell type implementation, thereby removing manufacturing barriers.
4Manufacturing precision
If a self-align contact layer is introduced in the cell array region, then the manufacturing precision is improved, but the device complexity increases
Solution Approach 1:
The self-align contact layer serves multiple functions simultaneously: it provides precise alignment in the cell array region, acts as a connection conduit to the conductive layers, and enables the formation of single stage cell type decoupling capacitors. By making this layer multi-functional, the patent reduces the need for additional separate structures, thereby limiting the increase in overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces resistance in the connection line, allows for the implementation of single stage cell type decoupling capacitors, and maximizes capacitance, effectively addressing the capacitance decrease issue in prior art devices.
Implementation Method 1
a power decoupling capacitor is formed in the semiconductor memory device to filter noise existing in an operating voltage, such as the power supply voltage (VDD) and the ground voltage (VSS)
Data Source
AI summary
Provided is a semiconductor memory device using a layout scheme where a bottom conductive layer in a peripheral circuit region, which is simultaneously formed with a self-align contact, is connected to one electrode of a power decoupling capacitor. Predetermined capacitors selected among a plurality of capacitors are connected to each other in parallel by using a conductive layer that is simultaneously formed with the self-align contact in a cell array region. Herein, the conductive layer and the self-align contact may be made of the same material. It is possible to embody the decoupling capacitor of a single stage cell type by connecting the conductive layer to a top interconnection layer. In addition, other embodiments implement the decoupling capacitor in a two-stage cell type by connecting a plurality of decoupling capacitors in series by means of the conductive layer in the peripheral circuit region.