Semiconductor Memory Device Defective Column Management
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Solution Overview
Problem
In NAND memory devices, write operations on defective columns can cause stress on bit lines, leading to inefficiencies and potential damage, as existing methods do not effectively manage defective columns during data transfer.
Innovation Solution
A semiconductor memory device design that includes a data bus, a data latch to identify defective columns, and a transistor configuration that keeps defective columns in a non-selected state during write operations, thereby preventing stress on bit lines by using a PMOS transistor to maintain a power supply voltage on the data bus when a column is identified as defective.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write operation is performed on defective columns using conventional methods, then data transfer can be completed, but stress is applied to bit lines causing potential damage and reduced reliability
Solution Approach 1:
The patent applies preliminary action by setting the sense amplifier latch to non-selected state before the actual write operation begins. The controller identifies defective columns in advance and pre-configures the sense amplifier latch accordingly, so that when the write operation starts, the bit line in the defective column is already protected from stress. This prevents bit line damage while maintaining write operation speed.
2Reliability
If conventional write operation method is used without defective column management, then write operation can be executed simply, but bit lines in defective columns are subjected to stress leading to potential failure
Solution Approach 1:
The patent introduces an intermediary mechanism - the sense amplifier latch - that mediates between the write operation control signals and the bit line. The sense amplifier latch acts as a buffer that can be configured to block or allow write signals to reach the bit line. By controlling the sense amplifier latch state based on defective column identification, the system protects bit lines from stress while maintaining a relatively simple overall control structure.
3Productivity
If defective columns are not properly managed during write operation, then data transfer speed can be maintained, but stress on bit lines causes inefficiencies and potential damage
Solution Approach 1:
The patent applies local quality by treating defective columns differently from normal columns. The sense amplifier latch is configured with column-specific control signals that identify which columns are defective. For defective columns, the latch is set to non-selected state to protect the bit line, while normal columns continue to operate normally. This localized differentiation protects bit lines from stress without affecting overall data transfer speed.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory cells, a data bus connected to a first column of the memory cells, by which data is transferred to and from the memory cells of the first column, a data latch storing data indicating whether the first column is defective or not, and a transistor having a first terminal connected to the data bus, a second terminal connected to a voltage source, and a gate connected to an output of the data latch.