3D Semiconductor Memory Device Integration Density
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Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited by the cost of expensive processing equipment required for forming fine patterns, making it difficult to increase their integration density without significantly increasing manufacturing costs.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a substrate with a cell array region and a contact region, including stack structures with gate electrodes, cell vertical channel structures, and a contact structure with varying heights and interlayer dielectric thicknesses, allowing for increased integration density while reducing equipment costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor memory devices are used, then manufacturing process is simpler, but integration density is limited due to expensive processing equipment requirements for fine patterns
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. The stack structure includes multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) stacked vertically, with channel structures extending through the stack, enabling increased integration density without requiring finer lateral patterning
2Manufacturing precision
If three-dimensional semiconductor memory devices are used, then integration density is increased, but device structure becomes more complex
Solution Approach 1:
The stack structure is divided into multiple distinct gate electrodes (first gate electrode, second gate electrode, third gate electrode) separated by insulating layers, with channel structures segmented into corresponding segments. This segmentation allows independent control and simplifies the fabrication process compared to a monolithic three-dimensional structure
Solution Approach 2:
The patent employs a nested structure where channel structures are surrounded by insulating layers, which are in turn surrounded by gate electrodes, with additional insulating layers and gate electrodes nested outside. This nested arrangement achieves high integration density while maintaining a systematic fabrication approach
Data Source
AI summary
A semiconductor memory device includes a substrate having a cell array region and a contact region, a stack structure including a plurality of gate electrodes on the cell array region and the contact region, a plurality of cell vertical channel structures extending through the stack structure on the cell array region, and a contact structure disposed beside of the stack structure on a top surface of the substrate and disposed along a line extending from the cell array region toward the contact region. The height of the contact structure on the cell array region is different from the height of the contact structure on the contact region.