Semiconductor Memory Device Etching Stop Layer UV Irradiation
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Solution Overview
Problem
The structural design and packaging of one-time programmable (OTP) non-volatile memory devices are limited by the requirement for ultraviolet (UV) irradiation, which can interfere with the etching stop layer's operation and affect the manufacturing process and electrical performance of semiconductor memory devices.
Innovation Solution
An opening is created in the etching stop layer to overlap with the floating gate electrode, allowing for UV irradiation while using the etching stop layer to absorb light and prevent interference with the floating gate electrode's operation, thereby enabling the etching stop layer to be used without influencing the semiconductor memory device's operating conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an etching stop layer is used in the manufacturing process, then the manufacturing precision is improved, but the ultraviolet irradiation operation is blocked and cannot reach the floating gate electrode
Solution Approach 1:
The etching stop layer is segmented by creating openings in it, allowing UV light to pass through specific regions while maintaining the layer's etching stop functionality in other areas. This segmentation resolves the contradiction by dividing the layer into functional zones.
Solution Approach 2:
The etching stop layer is designed with different properties in different locations: regions with openings allow UV transmission to the floating gate electrode, while solid regions maintain etching protection. This local differentiation resolves the contradiction between blocking UV and enabling etching.
2Object-affected harmful factors
If the etching stop layer is removed to allow UV irradiation, then the irradiation operation can be performed, but the manufacturing process loses the etching stop protection
Solution Approach 1:
Instead of removing the entire etching stop layer, openings are created in specific regions to allow UV irradiation while preserving the layer in other regions to maintain etching protection. This resolves the contradiction by selective removal.
Solution Approach 2:
The openings in the etching stop layer act as intermediaries that allow UV light to pass through to the floating gate electrode while the surrounding etching stop layer material continues to provide protection during manufacturing processes.
3Reliability
If UV irradiation is performed through the etching stop layer, then the floating gate electrode can be programmed, but the etching stop layer's process effect is compromised
Solution Approach 1:
The etching stop layer is segmented with openings positioned over the floating gate electrode regions, enabling UV irradiation to program the memory while maintaining the layer's structural integrity and etching stop function in non-opening areas.
Solution Approach 2:
The etching stop layer exhibits different optical properties locally: transparent regions (openings) allow UV transmission for programming, while opaque regions maintain etching protection. This local quality differentiation resolves the contradiction between programming reliability and manufacturing ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for successful UV irradiation of the floating gate electrode while maintaining the etching stop layer's functionality, enhancing manufacturing yield and avoiding negative impacts on the semiconductor memory device's performance.
Implementation Method 1
using the etching stop layer to absorb light and prevent interference with the floating gate electrode's operation
Data Source
AI summary
A semiconductor memory device includes a substrate, at least one floating gate electrode, an interlayer dielectric layer, an interconnection structure, an etching stop layer, a conductive structure, and an opening. The floating gate electrode is disposed on the substrate. The interlayer dielectric layer is disposed on the floating gate electrode. The interconnection structure is disposed in the interlayer dielectric layer. The etching stop layer is disposed on the interlayer dielectric layer. The conductive structure penetrates the etching stop layer and is electrically connected with the interconnection structure. The opening penetrates the etching stop layer and overlaps at least a part of the floating gate electrode in a thickness direction of the substrate.