Semiconductor Memory Device High Low Voltage Line Separation
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Solution Overview
Problem
Semiconductor memory devices face reliability deterioration due to electrical coupling between high voltage and low voltage wires, which affects their performance and reliability as the degree of integration increases, leading to potential electrical coupling issues.
Innovation Solution
The semiconductor memory device design includes a peripheral region with high voltage and low voltage lines that are sufficiently separated to prevent electrical coupling, with specific configurations of first and second lower lines and contacts ensuring that high voltage lines do not face low voltage lines along certain directions, maintaining a sufficient separation distance to avoid electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to achieve higher capacity and smaller chip size, then the chip size and device density are improved, but electrical coupling between high voltage and low voltage wires occurs causing reliability deterioration
Solution Approach 1:
The wire structure is segmented into multiple layers (first lower lines, second lower lines, first upper lines, second upper lines) with alternating high voltage and low voltage lines in different layers. This spatial segmentation prevents direct electrical coupling while maintaining high integration density.
Solution Approach 2:
The patent transitions from planar wire arrangement to three-dimensional multi-layer arrangement. High voltage and low voltage lines are separated in the vertical dimension (different layers) while maintaining horizontal connectivity, thus preventing electrical coupling without sacrificing integration.
2Area of stationary object
If high voltage lines and low voltage lines are arranged close together to reduce wire region size, then area is reduced, but electrical coupling occurs causing reliability deterioration
Solution Approach 1:
High voltage and low voltage lines are nested in an alternating pattern across multiple layers. Each layer contains both high and low voltage lines, with the next layer providing separation and continuation. This nested multi-layer structure achieves compact area while preventing electrical coupling through layer isolation.
Solution Approach 2:
The patent introduces intermediate structures (insulating layers, different wire layers) between high voltage and low voltage lines that are arranged adjacently. These intermediaries prevent direct electrical coupling while allowing the lines to maintain close spatial proximity for compact design.
3Reliability
If wire separation distance is increased to prevent electrical coupling, then electrical reliability is improved, but chip area increases
Solution Approach 1:
The patent resolves the area-reliability tradeoff by moving the separation distance into the vertical dimension (multiple layers) rather than increasing horizontal separation. This allows lines to be close in the plane while maintaining adequate separation through layer stacking, thus preventing electrical coupling without increasing chip area.
Solution Approach 2:
The wire routing is segmented across multiple layers with high voltage and low voltage lines alternating between layers. This segmentation allows adequate separation distance to be achieved vertically between adjacent high and low voltage lines while maintaining compact horizontal layout, thus preventing electrical coupling without increasing overall chip area.
Data Source
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AI summary
Disclosed are semiconductor memory devices comprising a peripheral region (100) including a substrate (110), high voltage transistors (112a) on the substrate (110), first lower lines (122) connected to the high voltage transistors (112a), and second lower lines (124) connected to the first lower lines (122), and a cell region (200) on the peripheral region (100). The first and the second lower lines (124) extend along a first direction (DR1) parallel to an upper surface of the substrate (110). The first lower lines (122) include first high voltage lines (122a) and first low voltage lines. The second lower lines (124) include second high voltage lines (124a) and second low voltage lines (124b). The second high voltage lines (124a) and the first low voltage lines (124b) are separated in a second direction (DR2) parallel to the upper surface of the substrate (110) and a third direction (DR3) perpendicular to the upper surface of the substrate (110), and the second low voltage lines (124b) and the first high voltage lines (122a) are separated in the second direction (DR2) and the third direction (DR3).