Semiconductor Memory Device With Overlying Decoupling Capacitor Array

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Solution Overview

Problem

Current semiconductor technologies face limitations in increasing integration density beyond two-dimensional formations due to physical constraints, necessitating innovative approaches to enhance chip performance and functionality.

Innovation Solution

A semiconductor structure incorporating a stacked one-time-programmable (OTP) device and a decoupling capacitor array, with specific layering and isolation techniques, including buried word lines, diffusion regions, and conductive layers, to optimize chip design and functionality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If two-dimensional integrated circuit formation is used, then manufacturing process is simple, but integration density cannot be increased further due to physical limitations

Engineering Contradiction:

Improveintegration densityVSAvoidstructural complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking by placing the decoupling capacitor array overlying the OTP device. This vertical arrangement allows multiple functional blocks to occupy different height levels, dramatically increasing integration density without proportionally increasing footprint area or manufacturing complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If decoupling capacitors are placed away from OTP device, then manufacturing is easier, but electrical isolation and current supply efficiency are reduced

Engineering Contradiction:

Improveelectrical isolation efficiencyVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the OTP device and decoupling capacitor array into a single stacked structure where the capacitor array is positioned directly overlying the OTP device. This integration achieves both electrical isolation through the inter-layer dielectric and efficient current supply through close proximity, while simplifying the overall manufacturing process by reducing the number of separate components and interconnections required.

Inventive Principle:

Principle #5Merging (Combining)

3Quantity of substance

If vertical stacking of OTP device and decoupling capacitor array is implemented, then integration density increases, but electrical isolation between components becomes more difficult

Engineering Contradiction:

Improveintegration densityVSAvoidelectrical interference

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an inter-layer dielectric as an intermediary layer positioned between the OTP device and the decoupling capacitor array in the vertical stack. This dielectric layer provides effective electrical isolation, preventing harmful electrical interference between the two functional blocks while allowing them to maintain close vertical proximity for high integration density.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10825823B1Semiconductor memory device including decoupling capacitor array arranged overlying one-time programmable device

Publication Date: 2020.11.03 NAN YA TECH

AI summary

The present disclosure provides a semiconductor chip. The semiconductor chip includes a substrate, a main device, a one-time-programmable (OTP) device and a decoupling capacitor array. The substrate includes a first region and a second region. The main device is in the first region, the OTP device and the decoupling capacitor array are in the second region, and the decoupling capacitor array overlies the OTP device.