Semiconductor Memory Device Parallel Sense Amplifier
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Solution Overview
Problem
NAND-type flash memory devices face limitations in high-speed random access due to small cell current, requiring data to be read out and serially output through a buffer to adapt to high-speed systems, and existing sense amplifiers struggle to detect small cell currents effectively.
Innovation Solution
A semiconductor memory device with first and second cell arrays, each having information and reference cells, utilizing three or more bit line pairs sharing a sense amplifier to detect cell current differences, and data latches to store and control write data, allowing for high-speed data read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If NAND-type flash memory uses voltage detecting type sense amplifier with precharged bit lines, then the structure is simple, but it cannot effectively detect small cell currents and achieve high-speed random access
Solution Approach 1:
The memory device is divided into multiple cell arrays (first and second cell arrays), each with its own bit line pairs. This segmentation allows parallel operation of multiple sense amplifiers, increasing overall detection capacity and speed while maintaining manageable complexity in each individual sense amplifier unit.
Solution Approach 2:
Reference cells are introduced as intermediary elements to generate reference currents that serve as comparison standards for detecting information cell currents. This intermediary mechanism enables precise differential detection by comparing unknown cell currents against known reference currents, significantly improving measurement precision.
2Speed
If data is read out to page buffer and then serially output, then high-speed system adaptability is improved, but access time increases and random access performance deteriorates
Solution Approach 1:
Data is pre-charged onto bit lines and held in data latches before being read out. This preliminary action allows multiple data elements to be prepared simultaneously in parallel, enabling faster access without requiring sequential buffering operations, thus reducing access time while maintaining high transmission rates.
Solution Approach 2:
The patent transitions from serial data output through a single buffer to parallel data paths with multiple bit line pairs and data latches. This dimensional change from 1D serial processing to 2D parallel processing enables simultaneous access to multiple data elements, dramatically improving random access performance.
3Device complexity
If multiple bit line pairs share a sense amplifier, then device complexity is reduced, but detection speed may be affected
Solution Approach 1:
The sense amplifier is designed as a universal component that can service multiple bit line pairs through time-multiplexed operation. This multi-functionality allows a single sense amplifier to perform detection on several bit line pairs sequentially, reducing the total number of sense amplifiers needed while maintaining adequate detection speed through efficient resource sharing.
Solution Approach 2:
The sense amplifier operates periodically, cycling through multiple bit line pairs in a systematic sequence. This periodic operation allows the single sense amplifier to cover multiple detection tasks over time, achieving the functionality of multiple amplifiers with fewer physical components while maintaining detection speed through optimized cycling patterns.
4Measurement precision
If voltage detecting type sense amplifier is used with precharged bit lines, then manufacturing is easier, but measurement precision of small cell currents is insufficient
Solution Approach 1:
Reference cells act as intermediary elements that generate stable reference currents, serving as a comparison baseline for measuring information cell currents. This intermediary approach transforms the difficult task of directly measuring tiny cell currents into a more manageable differential measurement problem, improving precision while keeping the circuit implementation relatively simple.
Solution Approach 2:
The patent changes the measurement parameter from absolute voltage detection to differential current comparison. By measuring the difference between information cell current and reference cell current, the system achieves higher precision in detecting small cell currents while maintaining ease of manufacture through standard differential circuit techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed data processing and storage by effectively detecting small cell currents and controlling bit line voltages, improving the adaptability of NAND-type flash memory to high-speed systems.
Implementation Method 1
a sense amplifier so shared by the bit line pairs as to sequentially detect cell current differences between the information cells and the reference cells coupled to the bit line pairs
Data Source
AI summary
A semiconductor memory device includes: first and second cell arrays each having electrically rewritable and non-volatile memory cells arranged, memory cells in the main parts serving as information cells used for storing data, the remaining parts as reference cells used for driving a reference current; three or more bit line pairs disposed in the first and second cell arrays, respectively; a sense amplifier so shared by the bit line pairs as to sequentially detect cell current differences between the information cells and the reference cells coupled to the bit line pairs; and first and second data latches arranged to store write data to be written into the first and second cell arrays, each number of the first and second data latches being equal to that of the bit line pairs, which share the sense amplifier and are simultaneously selected.