Semiconductor Memory Device Dynamic Data Routing for Defective Columns

Solution Overview

Problem

Conventional semiconductor memory devices face challenges in efficiently managing data transfer operations, particularly when defective column units are present, leading to reduced memory density and increased complexity in maintaining data integrity and access efficiency.

Innovation Solution

The semiconductor memory device employs a configuration with multiple column units and bus select circuits, where the sequencer controls global and local bus select switches to dynamically reroute data across available column units, ensuring continuous operation even with defective units by establishing alternative data transfer paths through global and local buses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional semiconductor memory devices manage data transfer operations with defective column units, then data integrity can be maintained, but memory density is reduced and device complexity increases

Engineering Contradiction:

Improvedata integrityVSAvoidcomplexity in managing data transfer

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic routing control where the sequencer selectively activates different switch elements (second switch element for normal operation, third switch element for defective column units) based on real-time column unit status. This dynamic reconfiguration allows the system to adapt to defects without requiring complex static redundancy structures, thereby maintaining data integrity while managing complexity through conditional, runtime decision-making rather than predetermined complex architecture

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent introduces switch elements (second and third switch elements) as intermediary components between the memory cell transistors and data bus. These switch elements act as mediators that can redirect data flow around defective column units, isolating defects from the data transfer path while maintaining continuous operation. The sequencer serves as another intermediary that coordinates the switching operations, managing the complexity of defect handling through centralized control logic

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If redundancy regions are added to handle defective column units, then reliability is improved, but area required for memory cell array increases

Engineering Contradiction:

Improveredundancy managementVSAvoidarea required for memory cell array

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent makes existing column units universal by enabling them to serve both normal and defective column unit functions through the switching mechanism. The same column unit can be accessed via the second switch element under normal conditions or via the third switch element when defective, eliminating the need for dedicated redundancy regions. This multi-functionality allows the system to handle defects using existing infrastructure, thereby improving reliability without increasing memory array area

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the operational parameters of existing column units rather than adding new physical structures. By modifying the routing parameters (which switch element is activated, which path data takes through the sequencer), the system can accommodate defective column units using the same physical memory cell transistors and data bus infrastructure, thus maintaining area efficiency while achieving redundancy functionality through parameter reconfiguration

Inventive Principle:

Principle #35Parameter changes

3Productivity

If data transfer paths are rerouted around defective column units, then productivity is maintained, but device complexity increases

Engineering Contradiction:

Improvedata input and output operationsVSAvoidcomplexity in data transfer routing

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic routing control where the sequencer selectively activates different switch elements (second switch element for normal operation, third switch element for defective column units) based on real-time column unit status. This dynamic reconfiguration allows the system to adapt to defects without requiring complex static redundancy structures, thereby maintaining data integrity while managing complexity through conditional, runtime decision-making rather than predetermined complex architecture

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system performs self-diagnosis and self-rerouting through the sequencer's ability to detect defective column units and automatically activate alternative data transfer paths using the third switch element. This self-service capability allows the memory device to maintain productivity by autonomously managing its own defect tolerance without requiring external intervention or complex external control mechanisms, thereby balancing productivity maintenance with controlled complexity

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS11461261B2Semiconductor memory device

Publication Date: 2022.10.04 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor memory device includes a first string including a first memory cell transistor and a second memory cell transistor which are coupled in series, a first switch element, a first latch circuit coupled in series between a first end of the first string and a first end of the first switch element, and a second switch element and a third switch element coupled in parallel between a second end of the first switch element and a data bus.