3D Semiconductor Memory Device Voids Prevention
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Solution Overview
Problem
Conventional semiconductor memory devices face physical limitations in reducing memory cell size, limiting their integration density, and there is a need for improved electrical characteristics in three-dimensional semiconductor memory devices.
Innovation Solution
A semiconductor memory device with insulating and conductive patterns stacked alternately, featuring penetrating structures and deposition suppressing layers to prevent voids in conductive patterns, allowing for efficient three-dimensional integration and enhanced electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase integration density, then integration density improves, but manufacturing precision deteriorates due to physical limits
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking of memory cells. Multiple layers of bit lines, word lines, and charge storage layers are stacked vertically to increase integration density without further reducing individual cell dimensions, thereby overcoming the physical limits of miniaturization while maintaining manufacturing precision.
Solution Approach 2:
The patent implements a nested structure where charge storage layers are surrounded by tunnel insulating layers, which are in turn surrounded by blocking insulating layers. Multiple functional layers are nested concentrically around the channel layer, enabling complex three-dimensional memory cell structures that achieve high integration density while maintaining precise manufacturing control through standardized layer formation processes.
2Reliability
If conductive patterns are formed in trenches to create gate electrodes, then device functionality improves, but voids form in the conductive patterns degrading electrical characteristics
Solution Approach 1:
The patent forms a deposition suppressing layer on the top surface of the trench before filling it with conductive material. This preliminary action prevents excessive conductive material deposition at the trench opening, which would otherwise create voids when the excess material is removed. The deposition suppressing layer controls the deposition process to achieve uniform filling without void formation, ensuring reliable electrical characteristics.
Solution Approach 2:
The deposition suppressing layer acts as an intermediary between the trench structure and the conductive material. It mediates the deposition process by preventing direct excessive deposition of conductive material at the trench opening, thereby eliminating the root cause of void formation while allowing complete filling of the trench interior.
Data Source
AI summary
A semiconductor memory device includes insulating patterns and conductive patterns stacked alternately with each other, penetrating structures passing through the insulating patterns and the conductive patterns, and deposition suppressing layers formed on one end portions of respective interfaces between the insulating patterns and the conductive patterns.