Semiconductor Memory Device Weak Erase Operation
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Solution Overview
Problem
In semiconductor memory devices, particularly NAND flash memory, the threshold voltage of MONOS cells decreases due to detrapping after a write operation, leading to increased write time as a countermeasure requires a verify operation and additional write pulses, which can hinder cache programming and data storage.
Innovation Solution
A semiconductor memory device with a memory cell array and data storage circuit that performs a first write operation, followed by a weak erase operation and a second write operation with verify steps, using read voltage levels and verify voltage levels to restore the threshold voltage and ensure high-speed writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a verify operation is performed after the first write sequence to address detrapping, then the threshold voltage stability is improved, but the write time increases
Solution Approach 1:
The patent applies preliminary action by performing a weak erase operation immediately after the first write sequence before the detrapping effect fully develops. This preliminary weak erase counteracts the detrapping and stabilizes the threshold voltage before subsequent write operations are needed, preventing the need for lengthy verify and rewrite cycles.
Solution Approach 2:
The patent extracts the harmful detrapping effect by introducing a weak erase operation that specifically targets and removes the trapped charges causing the threshold voltage decrease. This separation allows the main write operation to complete quickly while the weak erase handles the detrapping issue independently.
2Reliability
If additional write pulses are supplied to restore threshold voltage, then the threshold voltage stability is improved, but the device complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the erase operation parameters to create a 'weak erase' with reduced intensity compared to a full erase operation. This weak erase uses lower voltage or shorter pulse width to effectively counteract detrapping without causing excessive disturbance to the memory cells, thereby stabilizing threshold voltage without requiring complex multi-step rewrite procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the influence of threshold voltage fluctuations immediately after writing, enabling high-speed writing and maintaining data integrity by restoring the threshold voltage through a second write operation.
Implementation Method 1
Electrons are extracted from the memory cells by an erase operation to negatively set a threshold voltage, and the electrons are introduced into the memory cells by a write operation, whereby the threshold voltage is positively set.
Implementation Method 2
a threshold value Vth of the MONOS cells decreases due to detrapping immediately after a write operation
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.