Stacked Semiconductor Memory Arrays Beyond Die Area Limits
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited by the cost of fine pattern formation technology and the area of chip dies, which affects economic feasibility and performance.
Innovation Solution
A semiconductor memory device with a stacked structure comprising a peripheral circuit and multiple cell array structures, where each cell array is vertically stacked, featuring stepped and tapered conductive plate structures to increase integration and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional memory devices use fine pattern formation technology to increase integration, then the degree of integration improves, but the cost of equipment and chip die area increases significantly
Solution Approach 1:
The patent transitions from two-dimensional memory device layout to a three-dimensional stacked structure. Multiple cell array structures are vertically stacked on the peripheral circuit structure, with bonding pads electrically connecting different stacked layers. This vertical stacking enables higher integration without requiring proportionally larger chip die area or more expensive fine pattern formation equipment, as the integration increase comes from the third dimension rather than lateral scaling.
2Productivity
If two-dimensional memory devices increase degree of integration, then performance improves, but the degree of integration remains limited due to chip die area constraints
Solution Approach 1:
The patent employs vertical stacking of multiple cell array structures on the peripheral circuit structure, utilizing the third dimension to achieve higher integration. The bonding pads on different stacked layers provide electrical connections, enabling compact three-dimensional integration that dramatically increases the number of memory cells per unit chip die area, overcoming the limitations of two-dimensional scaling.
3Ease of manufacture
If vertical stacked structure is used to increase integration, then the need for fine pattern formation is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory device into distinct functional modules: a peripheral circuit structure and multiple cell array structures stacked thereon. Each cell array structure contains memory cells, conductive plate structures, and insulating layers. This segmentation into standardized stacked modules simplifies manufacturing by allowing repeated patterning processes rather than complex custom fine pattern formation, while the modular design manages overall device complexity.
Solution Approach 2:
By moving to three-dimensional stacking, the patent reduces reliance on expensive two-dimensional fine pattern formation technology. The vertical architecture allows standardization of cell array structures that can be replicated through stacking, simplifying the manufacturing process despite the increased vertical complexity, as each layer follows a consistent pattern.
Data Source
AI summary
In some embodiments, a semiconductor memory device includes a peripheral circuit structure, and a first and a second cell array structure. The peripheral circuit structure includes a circuit board, a peripheral circuit on the circuit board, a first insulating layer, and a plurality of first bonding pads on the first insulating layer. The first cell array structure includes a first memory cell array, a first conductive plate structure, a second insulating layer, and pluralities of second and third bonding pads on the second insulating layer. The second cell array structure includes a second memory cell array, a second conductive plate structure, a third insulating layer, and a plurality of fourth bonding pads on the third insulating layer. The first cell array structure and the second cell array structure are sequentially stacked in a vertical direction on the peripheral circuit structure.