Semiconductor Memory Device Discharge Transistor Source Line Control
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Solution Overview
Problem
Existing semiconductor memory devices with vertical channel structures face challenges in efficiently connecting cell strings to a source line without a source select transistor, which complicates manufacturing and can cause disturbances during read and program operations.
Innovation Solution
A semiconductor memory device is designed with a substrate having a CMOS circuit, a gate stacked body with interlayer insulating layers and conductive patterns, and channel structures passing through the gate stacked body. The device includes a bit line, cell strings coupled to the bit line, and a discharge unit between the source line and the cell strings, allowing each cell string to be selectively connected to the source line through a discharge transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a source select transistor is used to connect cell strings to the source line, then the connection can be controlled, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The invention extracts and removes the source select transistor from the conventional memory cell structure. By eliminating this component, the patent reduces device complexity and manufacturing difficulty while maintaining the essential function of connecting cell strings to the source line through the discharge transistor alone
Solution Approach 2:
The discharge transistor is designed to perform multiple functions: it serves both as the connection control element between cell strings and the source line, and as part of the read/program operation control. This multi-functionality eliminates the need for a separate source select transistor, reducing overall device complexity
2Reliability
If a source select transistor is used, then connection control is achieved, but manufacturing process becomes more complex
Solution Approach 1:
The invention extracts and removes the source select transistor from the conventional memory cell structure. By eliminating this component, the patent reduces device complexity and manufacturing difficulty while maintaining the essential function of connecting cell strings to the source line through the discharge transistor alone
3Productivity
If conventional vertical channel structure is used, then high integration is achieved, but disturbances occur during read and program operations
Solution Approach 1:
The invention introduces a discharge transistor as an intermediary element between the cell strings and the source line. This intermediary component enables precise control of the discharge path during read and program operations, preventing disturbances while maintaining the high integration density of the vertical channel structure
Solution Approach 2:
The discharge transistor provides dynamic control over the connection between cell strings and the source line, allowing the system to adaptively manage current flow during different operation modes (read, program, erase). This dynamic control prevents unwanted disturbances while maintaining high integration
Data Source
AI summary
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a substrate with a complementary metal oxide semiconductor (CMOS) circuit; a gate stacked body with interlayer insulating layers and conductive patterns that are alternately stacked on the substrate in a vertical direction; a plurality of channel structures passing through the gate stacked body, each with a first end that protrudes above the gate stacked body; and a plurality of conductive layers disposed over the gate stacked body. Each of the plurality of conductive layers is in contact with the first end of at least one of the plurality of channel structures.