Semiconductor Memory Device Dopant Distribution for Grain Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in optimizing the size of crystal grains in semiconductor layers, which affects the electric resistance and off-leakage current, limiting their performance.
Innovation Solution
The semiconductor memory device incorporates a manufacturing method involving the formation of semiconductor layers with specific dopant concentrations and crystal grain sizes, where the semiconductor layer contains crystal grains of 100 nm or more, and the dopant concentration is strategically distributed to reduce crystal grain boundary resistance and off-leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the crystal grain size in the semiconductor layer is increased, then the electric resistance in the ON state is reduced, but the manufacturing precision and control of crystal grain size become more difficult
Solution Approach 1:
The patent applies parameter changes by systematically varying dopant concentration, deposition temperature, and annealing conditions to control crystal grain size. Specifically, the semiconductor layer is formed with dopant concentrations of 1×10^19 to 1×10^21 atoms/cm³, and annealing is performed at 200°C to 400°C to promote crystal grain growth to 100 nm or more while maintaining manufacturing control
Solution Approach 2:
The patent implements local quality by creating specific dopant concentration distributions within the semiconductor layer. The dopant concentration is optimized in different regions to promote crystal grain growth at grain boundaries while maintaining appropriate conductivity in the bulk material, enabling selective control of crystal grain characteristics
2Reliability
If the dopant concentration in the semiconductor layer is increased, then the electric resistance is reduced, but the off-leakage current increases
Solution Approach 1:
The patent applies local quality by optimizing dopant concentration distribution within the semiconductor layer. The dopant concentration is set to 1×10^19 to 1×10^21 atoms/cm³, with specific regional variations that promote crystal grain growth at boundaries while maintaining appropriate conductivity in the bulk, thereby reducing resistance without proportionally increasing off-leakage current
Solution Approach 2:
The patent employs composite material strategies by combining the semiconductor layer with specific dopant distributions and crystal grain structures. The semiconductor layer contains crystal grains of 100 nm or more with controlled dopant concentrations, creating a composite structure that achieves low resistance while suppressing off-leakage current through the crystalline structure
3Reliability
If the crystal grain size is increased to reduce crystal grain boundary resistance, then the on-state performance improves, but the manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by incorporating dopants during the semiconductor layer formation process itself, rather than requiring separate post-processing steps. The dopant concentration is optimized at formation to promote crystal grain growth during subsequent annealing at 200°C to 400°C, achieving large crystal grains through a streamlined process that reduces manufacturing complexity
Solution Approach 2:
The patent uses parameter changes by optimizing the annealing temperature range (200°C to 400°C) and dopant concentration (1×10^19 to 1×10^21 atoms/cm³) to achieve crystal grain growth to 100 nm or more. These parameter optimizations enable crystal grain control through standard manufacturing processes without requiring complex additional equipment or steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the size of crystal grains to 100 nm or more, reducing electric resistance in the ON state and off-leakage current in the OFF state, thereby improving the overall performance of the memory cells.
Implementation Method 1
the first semiconductor layer contains crystal grains of 100 nm or more in size
Implementation Method 2
containing a dopant... when a concentration of the dopant in the first semiconductor layer is measured
Data Source
AI summary
A semiconductor memory device includes first conducting layers and a first semiconductor layer opposed to the first conducting layers. If a concentration of the dopant in the first semiconductor layer is measured along an imaginary straight line, the concentration of the dopant has: a maximum value at a first point, a minimum value in a region closer to the first conducting layer than the first point at a second point; and a minimum value in a region farther from the first conducting layer than the first point at a third point. The second point is nearer to an end portion of the first semiconductor layer on the first conducting layer side than that on the opposite side. The third point is farther from the end portion on the first conducting layer side than that on the opposite side.