Semiconductor Memory Device Dual Damascene Wiring

The patent divides the bit line and source line formation into separate damascene processes. The bit line is formed in a first damascene process with its own trench and fill sequence, while the source line is formed in a second damascene process with separate trench formation and copper filling. This segmentation eliminates the need for self-alignment between the two lines, reducing process complexity while maintaining manufacturing precision through independent process control.

The patent transitions from planar self-aligned formation to a three-dimensional separated damascene approach. By forming bit and source lines in separate trenches at different spatial locations and filling them in separate processes, the invention achieves miniaturization without relying on lithographic self-alignment. This dimensional separation allows independent optimization of each line's formation process, maintaining precision at sub-30nm scales.

The patent segments the dual damascene process into distinct stages: first forming the bit line trench and filling it with copper, then forming the source line trench and filling it with copper. Each trench is defined by separate mask patterns and etching processes, allowing independent precision control. This segmentation maintains manufacturing precision while achieving ease of manufacture through standardized repeated processes.