Semiconductor Memory Dual-Phase Erase for Data Reliability

The patent segments the erase operation into two distinct phases: a first erase operation that erases memory cells to a pre-erase state, and a second erase operation that selectively erases specific memory cells to a target erase state. This segmentation allows the memory device to maintain nonvolatile characteristics for data retention while optimizing write speeds by performing selective erasure only where needed, rather than erasing entire blocks.

The first erase operation serves as a preliminary action that prepares memory cells by erasing them to a pre-erase state before the actual programming operation. This preliminary erasure ensures that memory cells are in a known state ready for programming, improving subsequent write speeds while maintaining the reliability benefits of nonvolatile memory.

The patent applies partial action by performing the second erase operation selectively on only those memory cells that require erasure to the target erase state, rather than erasing all memory cells in the block. This selective approach ensures data reliability for cells that need it while minimizing the time penalty by avoiding unnecessary erasure operations on cells that don't require it.

The patent implements local quality by applying different erase states to different memory cells based on their specific requirements. The first erase operation applies to all memory cells in a block to establish a pre-erase state, while the second erase operation applies locally only to specific memory cells that need to reach the target erase state, optimizing both reliability and operation time.