Semiconductor Memory Device Dual Verify Programming Method
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in efficiently programming and verifying multiple states due to the need for extensive verification processes, which can increase programming time and potentially widen threshold voltage distributions, especially in multi-level cell configurations.
Innovation Solution
Implementing a dual verify method with primary and secondary program operations, where primary operations use multiple verification voltages for states below the highest threshold and a single verification voltage for the highest threshold state, followed by a reprogram operation using a secondary verification voltage for the highest threshold state, to optimize programming efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple verification steps are performed for each program state, then programming reliability is improved, but programming time increases
Solution Approach 1:
The verification process is segmented into different stages: first verification for lower program states and second verification for higher program states. This segmentation allows the system to apply appropriate verification intensity to each state, ensuring reliability while reducing overall verification time compared to uniform multi-step verification for all states.
Solution Approach 2:
Different verification strategies are applied to different program states based on their characteristics. Lower program states use one verification approach while higher program states use another, optimizing the balance between reliability and time for each specific state rather than applying a single verification method to all states.
2Reliability
If extensive verification processes are used, then programming reliability is improved, but threshold voltage distribution widens
Solution Approach 1:
The verification process is divided into stages with different verification voltages and criteria for different program states. This segmentation prevents excessive verification stress on memory cells, thereby maintaining tighter threshold voltage distributions while still ensuring programming reliability through state-appropriate verification.
Solution Approach 2:
Different verification parameters and thresholds are applied to different program states based on their specific characteristics. This localized verification approach ensures each state is verified adequately without subjecting all cells to uniform intensive verification that would widen threshold voltage distributions.
3Device complexity
If uniform verification is applied to all program states, then verification simplicity is maintained, but programming efficiency decreases
Solution Approach 1:
The verification process is segmented into different stages with different verification approaches for different program states. While this increases process complexity compared to uniform verification, it significantly improves programming efficiency by optimizing verification intensity for each state, reducing unnecessary verification steps.
Solution Approach 2:
The verification process transitions from a static uniform approach to a dynamic state-dependent approach. The verification parameters and intensity are adjusted dynamically based on the program state being verified, improving overall programming efficiency while maintaining manageable complexity through systematic state-based differentiation.
Data Source
AI summary
A semiconductor memory device in accordance with an embodiment may include a memory cell array, a peripheral circuit, and a control circuit. The memory cell array may include a plurality of memory cells programmed to any one of first to N-th program states divided based on threshold voltages. The peripheral circuit may perform a program operation on the memory cells. The control circuit may control the peripheral circuit so that, during the program operation, a primary program operation is performed, and after the primary program operation, a secondary program operation is performed. The primary program operation may include a plurality of verify steps performed for the first to N-1-th program states and a single primary verify step performed for the N-th program state. The secondary program operation may include a secondary verify step performed for the N-th program state.