3D Semiconductor Memory Device Dummy Block Global Row Line Sharing
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Solution Overview
Problem
The existing semiconductor memory devices of two-dimensional structures have reached integration limits, prompting the need for three-dimensional structures to increase memory density, but they face challenges in efficiently utilizing space and reducing size while maintaining performance.
Innovation Solution
A semiconductor memory device with a three-dimensional structure is designed, featuring first and second memory blocks with alternately stacked conductive and dielectric layers, channel structures, and a dummy block that allows for efficient placement of pass transistors and global row lines, reducing the number of pass transistors and wiring lines by sharing global row lines and optimizing the use of space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional structure with multiple memory blocks is used to increase memory density, then the storage capacity is improved, but the number of pass transistors and wiring lines increases, leading to increased device complexity and size
Solution Approach 1:
The patent merges the control of multiple memory blocks by introducing a dummy block that allows bottom global row lines to be shared across multiple memory blocks. The top global row lines formed over the dummy block and coupled to bottom global row lines through contact plugs enable unified control signaling, reducing the total number of separate wiring lines and pass transistors needed to manage multiple memory blocks in the three-dimensional structure.
Solution Approach 2:
The dummy block serves multiple functions: it provides a platform for forming top global row lines, enables sharing of bottom global row lines among multiple memory blocks, and facilitates the connection between top and bottom global row lines through contact plugs. This multi-functional structure reduces overall device complexity while maintaining high memory density.
2Volume of moving object
If more memory blocks are stacked vertically to increase integration, then the storage capacity is improved, but the wiring complexity and device area increase
Solution Approach 1:
The patent utilizes vertical stacking of memory blocks to increase storage capacity within a smaller footprint. By forming bottom global row lines in a bottom wiring layer below the semiconductor layer and top global row lines over the dummy block, the design efficiently uses the vertical dimension for wiring routing, reducing the horizontal area required for interconnects while maintaining high integration.
Data Source
AI summary
A semiconductor memory device includes first and second memory blocks each including conductive and dielectric layers alternately stacked over a semiconductor layer disposed over a substrate, and disposed adjacent to each other in a first direction; a dummy block disposed over the semiconductor layer, and provided between the first and second memory blocks; first pass transistors formed over the substrate below the first memory block, and coupled to conductive layers, respectively, of the first memory block; second pass transistors formed over the substrate below the second memory block, and coupled to conductive layers, respectively, of the second memory block; bottom global row lines between the first and second pass transistors and the semiconductor layer, and each coupled to one of the first pass transistors and one of the second pass transistors; and top global row lines formed over the dummy block, and coupled to the bottom global row lines.