Semiconductor Memory Device with Dummy Cells for Bad Cell Replacement
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Solution Overview
Problem
Semiconductor memory devices face challenges in managing bad memory cells, which can lead to reduced storage space and reliability due to local bridges causing unintended voltage changes, affecting program and read operations.
Innovation Solution
The implementation of a semiconductor memory device with a memory cell array that includes both normal and dummy memory cells in a stacked configuration, where bad memory cells are replaced with dummy cells to maintain storage space and reliability, using specific voltage applications during program, read, and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bad memory cells are removed from the memory cell array, then reliability is improved, but storage space is reduced
Solution Approach 1:
The patent creates dummy memory cells that are copies of normal memory cells but are not connected to normal word lines. These dummy cells serve as replacements for bad memory cells, allowing the system to maintain the original memory array structure and storage capacity while isolating and replacing defective cells with functional dummy cells that have the same physical characteristics but different electrical connectivity.
Solution Approach 2:
The patent introduces dummy memory cells as intermediary elements between the bad memory cells and the rest of the memory system. These dummy cells act as mediators that can be electrically isolated from normal word lines during programming operations, preventing voltage interference while maintaining the appearance of a complete memory array to external systems.
2Ease of operation
If voltage is applied to normal word lines during program operation, then program operation is enabled, but unintended voltage changes occur in bad memory cells
Solution Approach 1:
The patent segments the word line system into two distinct groups: normal word lines that connect to normal memory cells and dummy word lines that connect to dummy memory cells. This segmentation allows independent voltage control, where normal word lines can be programmed without causing unintended voltage changes in dummy memory cells, as they are electrically isolated through different word line connections.
Solution Approach 2:
The patent applies different voltage characteristics to different parts of the memory array. Normal word lines receive programming voltages for normal memory cells, while dummy word lines are controlled separately to prevent unintended voltage changes. This local differentiation ensures that voltage applications are tailored to the specific needs of each memory cell type, preventing interference between normal and dummy cells.
Data Source
AI summary
The semiconductor memory device includes a memory cell array including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked configuration over a substrate, a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells, and a second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells, wherein the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cells are is replaced with a dummy memory cell from among the second plurality of dummy memory cells.