Semiconductor Memory Device Dummy Gate Leakage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in effectively managing the resistance states of variable resistance elements, leading to issues with data retention and leakage currents, particularly in three-dimensional memory architectures.
Innovation Solution
The semiconductor memory device incorporates a variable resistance layer between word line conductive layers and a semiconductor layer, with a dummy gate insulating layer and a comb-shaped dummy word line conductive layer to control resistance and suppress leakage currents, using metal oxide films and specific materials like hafnium oxide and polysilicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a variable resistance element is employed as a storage element in three-dimensional memory architecture, then memory capacity can be increased, but leakage currents increase and data retention deteriorates
Solution Approach 1:
A dummy gate insulating layer is introduced as an intermediary between the word line conductive layer and the semiconductor layer. This dummy gate insulating layer acts as a mediator to control and suppress leakage currents that flow through the variable resistance element, thereby resolving the contradiction between maintaining high memory capacity and reducing harmful leakage currents.
Solution Approach 2:
The word line structure is segmented into a real word line conductive layer and a dummy gate conductive layer, with the dummy gate insulating layer separating them. This segmentation allows independent control of the dummy gate to suppress leakage currents while the real word line maintains memory storage function, thus addressing the leakage issue without compromising memory capacity.
2Quantity of substance
If a variable resistance element is employed as a storage element in three-dimensional memory architecture, then memory capacity can be increased, but data retention deteriorates
Solution Approach 1:
The dummy gate insulating layer serves as an intermediary that prevents unwanted electrical interactions between the word line and semiconductor layer. By controlling leakage currents through this intermediary layer, the stability of resistance states in variable resistance elements is improved, thereby enhancing data retention while maintaining high memory capacity.
Solution Approach 2:
The dummy gate insulating layer is prepared in advance as a protective barrier before data storage operations. This prior cushioning structure prevents leakage currents from developing during storage, thereby protecting data retention from deterioration while maintaining the high capacity benefits of three-dimensional architecture.
3Device complexity
If conventional structures are used without dummy gate, then device complexity is reduced, but leakage current control and data retention are insufficient
Solution Approach 1:
A dummy gate insulating layer and dummy gate conductive layer are introduced as intermediary structures. While these additions increase device complexity, they provide essential control over leakage currents and improve data retention. The dummy gate structure acts as a mediator that enables reliable data storage without requiring complex control circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data retention by controlling resistance values and reducing leakage currents, improving the overall performance and reliability of the memory device.
Implementation Method 1
a variable resistance layer provided between the word line conductive layer and the semiconductor layer
Implementation Method 2
a dummy gate insulating layer extending in a first direction with respect to the semiconductor layer
Data Source
AI summary
According to an embodiment, a semiconductor memory device comprises: a first semiconductor layer extending in a first direction; a first wiring line extending in a second direction intersecting the first direction; a variable resistance layer provided between these first wiring line and first semiconductor layer; and a first gate electrode extending in the first direction and facing the first semiconductor layer via a first insulating layer. In addition, this semiconductor memory device comprises a second gate electrode provided in the first direction with respect to the first wiring line, extending in the second direction in parallel to the first wiring line, and facing the first semiconductor layer. This second gate electrode faces the first semiconductor layer via a second insulating layer. Moreover, this second gate electrode faces the first gate electrode via the second insulating layer, the first semiconductor layer, and the first insulating layer.