Semiconductor Memory Device Dummy Pillar Leakage Current

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Solution Overview

Problem

The integration of two-dimensional semiconductor devices is limited due to the high cost of equipment needed for forming fine patterns, and three-dimensional semiconductor memory devices are developed to overcome this, but they face challenges in reliability and efficiency.

Innovation Solution

A semiconductor memory device with a substrate having a cell array and pad region, featuring a stack structure with gate electrodes, a device isolation layer, a dummy vertical channel portion, and a dummy semiconductor pillar, which enhances reliability by preventing leakage current and electrical connection to the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If three-dimensional semiconductor memory devices are developed to overcome integration limitations, then integration capability is improved, but reliability deteriorates due to leakage current and electrical connection issues

Engineering Contradiction:
Improveintegration capabilityVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A dummy semiconductor pillar is introduced as an intermediary structure between the dummy vertical channel portion and the substrate. This pillar acts as a mediator to prevent direct electrical connection between the dummy channel and substrate, thereby blocking leakage current paths while maintaining the structural integrity needed for high integration. The intermediary pillar resolves the contradiction by enabling both high integration and improved reliability through its mediating function.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The harmful electrical connection between the dummy vertical channel portion and the substrate is extracted or removed by introducing the dummy semiconductor pillar. The pillar creates an isolated structure where the dummy channel is separated from the substrate, extracting the problematic direct connection while preserving the beneficial dummy channel structure for integration purposes.

Inventive Principle:
Principle #2Taking out (Extraction)

2Strength

If substrate contact is made for structural support, then mechanical stability is improved, but leakage current and voltage interference increase

Engineering Contradiction:
Improvemechanical stabilityVSAvoidelectrical characteristics
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The dummy semiconductor pillar acts as a mediator that provides mechanical support (maintaining structural stability) while simultaneously preventing direct electrical contact between the dummy vertical channel portion and the substrate. This intermediary structure resolves the contradiction by decoupling the mechanical and electrical functions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The structural support function is segmented from the electrical connection function by introducing the dummy semiconductor pillar. The pillar provides mechanical stability while the spacing between the dummy channel and substrate prevents electrical interference, segmenting the two functions into separate spatial zones.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10950619B2Semiconductor memory device
Publication Date: 2021.03.16 SAMSUNG ELECTRONICS CO LTD
  • US10950619B2 patent drawing
  • US10950619B2 patent drawing
  • US10950619B2 patent drawing

AI summary

A semiconductor memory device includes a substrate including a cell array region and a pad region, a stack structure disposed on the cell array region and the pad region of the substrate and including gate electrodes, a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate, a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer, and a dummy semiconductor pillar disposed between the dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.