Semiconductor Memory Device Dummy Source Plate ESD Shielding
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Solution Overview
Problem
Semiconductor memory devices are vulnerable to electrostatic discharge (ESD) damage, which can destroy components like diodes and transistors, and existing solutions do not adequately protect against ESD without increasing manufacturing complexity and cost.
Innovation Solution
A semiconductor memory device design that includes a logic circuit with a dummy source plate maintained at a constant voltage, acting as an ESD shield, separates the source plate into cell and dummy source plates with a slit, and incorporates an electrostatic discharge shield plate over the logic circuit, effectively shielding it from ESD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate ESD shielding structure is added to protect the logic circuit, then ESD protection capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The source plate is designed to serve dual functions: as an electrical connection component for memory cell operations and as an ESD shielding structure. By maintaining the source plate at a constant potential through connection to a reference potential line, it simultaneously provides its original function and protects the logic circuit from ESD, eliminating the need for separate shielding structures.
Solution Approach 2:
The invention merges the ESD shielding function with the existing source plate structure. Instead of adding a separate shielding layer, the source plate itself is configured to provide ESD protection by connecting it to a reference potential, thereby combining multiple functions into a single existing component.
2Reliability
If ESD protection measures are implemented, then reliability against electrostatic discharge is improved, but manufacturing cost increases
Solution Approach 1:
The source plate performs both its original function of electrical connection for memory cells and an additional ESD protection function. This multi-functionality eliminates the need for separate ESD protection components, reducing manufacturing steps and costs while maintaining reliability.
Solution Approach 2:
The source plate automatically provides ESD protection through its inherent structure and connection to the reference potential line, without requiring additional active protection mechanisms or complex control systems. The constant potential maintenance inherently shields the logic circuit.
3Reliability
If the source plate is separated into cell source plate and dummy source plate with a slit, then ESD shielding effectiveness is improved, but device complexity increases
Solution Approach 1:
The source plate is segmented into a cell source plate and a dummy source plate separated by a slit. This segmentation allows the dummy source plate to specifically target and shield the logic circuit region from ESD while the cell source plate maintains normal memory cell connections, providing localized protection without compromising overall functionality.
Solution Approach 2:
The dummy source plate is positioned specifically over the logic circuit region to provide localized ESD protection where it is most needed. The slit configuration creates a localized shielding effect targeted at the vulnerable logic circuit while leaving other areas unaffected, optimizing protection efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces ESD-induced damage to the logic circuit by maintaining the dummy source plate at a constant voltage, suppressing ESD and improving electrical characteristics while simplifying manufacturing and reducing costs by eliminating the need for separate shielding structures.
Implementation Method 1
a dummy source plate in the peripheral region. The dummy source plate may be maintained at a constant voltage independent of operations the memory cell array and the logic circuit
Data Source
AI summary
A semiconductor memory device includes a logic circuit disposed on a substrate having a cell region and a peripheral region outside the cell region; a source plate defined over the logic circuit; a slit separating the source plate into a cell source plate in the cell region and a dummy source plate in the peripheral region; and a memory cell array defined on the cell source plate. The dummy source plate is maintained at a constant voltage independent of operations of the memory cell array and the logic circuit.