3D Semiconductor Memory Device With Dummy Via Plugs
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Solution Overview
Problem
Current semiconductor memory devices face limitations in achieving high integration density due to the high cost and limitations of equipment for forming fine patterns, leading to the development of three-dimensional structures to enhance memory capacity at reasonable costs.
Innovation Solution
A semiconductor memory device design featuring a substrate with vertical pillars, connection lines, and via plugs in the cell region, along with a dummy connection line and via plug in the dummy region, which are electrically isolated, allowing for increased integration density without the need for expensive equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If equipment for forming fine patterns is used to increase integration density, then integration density is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical structures by stacking multiple memory cell layers vertically. This dimensional change allows integration density to increase without requiring proportionally finer pattern formation equipment, as the density gain comes from the vertical stacking dimension rather than horizontal pattern refinement alone.
Solution Approach 2:
The memory device is divided into multiple segmented memory cell layers stacked vertically, with each layer containing memory cells, connection lines, and via plugs. This segmentation allows the integration density to be increased through stacking while using standard pattern formation equipment for each individual layer, avoiding the need for extremely expensive ultra-fine pattern equipment.
2Reliability
If dummy structures are added to improve manufacturing uniformity, then reliability is improved, but device complexity increases
Solution Approach 1:
Dummy connection lines and dummy via plugs are created as simplified copies of the actual connection lines and via plugs. These dummy structures replicate the geometric patterns and material compositions of the functional structures, allowing uniform processing conditions across the entire wafer during manufacturing, thereby improving reliability without adding significant complexity.
Solution Approach 2:
The dummy structures are designed to have the same material composition, layer stacking sequence, and geometric characteristics as the functional memory structures. This homogeneity ensures that all regions of the substrate experience identical processing conditions during manufacturing steps, improving uniformity and reliability while maintaining relatively simple device architecture.
Data Source
AI summary
A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.