Semiconductor Memory Dynamic Bit Processing Power Reduction

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Solution Overview

Problem

Semiconductor memory devices experience high power consumption during write and read operations due to a fixed number of bits being processed, leading to increased energy usage in memory systems and electronic devices.

Innovation Solution

A semiconductor memory device that processes mode set codes and data bit number information to dynamically adjust the number of bits processed during operations, using a control device to generate data signals for write and read commands, and a memory cell array to input or output data based on selected memory cells, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a fixed number of bits is processed during write and read operations, then data consistency is maintained, but power consumption increases

Engineering Contradiction:
Improvepower consumptionVSAvoidflexibility in bit processing
Core Design Contradiction:
Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic bit processing by enabling the semiconductor memory device to flexibly adjust the number of bits processed during write and read operations based on external commands. The control device receives a command indicating a data bit number and processes only that specific number of bits, allowing the system to adapt between processing 1 bit or multiple bits per operation. This dynamic approach resolves the contradiction by making the bit processing quantity variable rather than fixed, thereby reducing unnecessary power consumption while maintaining operational flexibility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of data bit number from a fixed value to a variable parameter that can be dynamically adjusted through external commands. The control device processes a command containing data bit number information and accordingly adjusts the number of bits input to or output from memory cells. This parameter change enables the system to optimize power consumption by processing only the required number of bits, directly addressing the technical contradiction between energy efficiency and adaptability.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the number of bits processed is increased, then data throughput improves, but power consumption increases

Engineering Contradiction:
Improvedata throughputVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by allowing the system to process only the necessary number of bits required for each operation, rather than always processing the maximum number of bits. The control device receives commands specifying data bit numbers and processes exactly that many bits, enabling partial processing when full bandwidth is not needed. This resolves the contradiction by matching the processing quantity to actual requirements, improving energy efficiency while maintaining the capability for high throughput when necessary.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10908827B2Semiconductor memory devices, and memory systems and electronic apparatuses having the same
Publication Date: 2021.02.02 SAMSUNG ELECTRONICS CO LTD
  • US10908827B2 patent drawing
  • US10908827B2 patent drawing
  • US10908827B2 patent drawing

AI summary

A semiconductor memory device is configured to input a mode set code and set data on-the-fly in response to a mode set command, process data bit number information a write command to generate a first data signal, process data bit number information with a read command to generate a second data signal in response to the data on-the-fly indicating an enabled state, access a selected memory cell based on a word line selection signal generated using a row address and active command and a column selection signal generated using a column address and write command or read command, process a first quantity of data bits and transmit the first quantity of data bits to the selected memory cell in response to the first data signal, and process data received from the selected memory cell and output a second quantity of data bits in response to the second data signal.