Semiconductor Memory Device Dynamic Timing Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional OneNAND semiconductor memory devices face challenges in increasing clock frequency during clock synchronous burst read operations, particularly when the start address is a last column address, due to fixed timing settings for data latch and address counting that do not account for different bank structures.
Innovation Solution
The semiconductor memory device incorporates a control circuit that adjusts the timing of starting address counting and data storage in data latches based on the bank structure and read latency signal during clock synchronous burst read operations, allowing for flexible timing settings tailored to specific buffer memory configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed timing settings are used for data latch and address counting, then device complexity is reduced, but clock frequency cannot be increased during burst read operations
Solution Approach 1:
The patent implements dynamic timing adjustment by making the data latch timing and address counting timing variable based on the bank structure of the buffer memory. The control circuit automatically adjusts these timings according to whether a one-bank or two-bank structure is detected, enabling the system to optimize clock frequency dynamically without increasing overall device complexity.
2Speed
If timing is optimized for one-bank structure, then read speed improves for one-bank buffers, but two-bank buffers cannot achieve maximum clock frequency
Solution Approach 1:
The patent changes the timing parameters dynamically based on the bank structure parameter. The control circuit detects the bank structure (one-bank or two-bank) and adjusts the data latch timing and address counting timing accordingly, allowing the system to achieve optimal read speed for each specific buffer configuration without sacrificing compatibility.
3Speed
If automatic timing adjustment based on bank structure is implemented, then clock frequency can be increased for all buffer types, but control circuit complexity increases
Solution Approach 1:
The control circuit performs preliminary detection of the bank structure before executing burst read operations. By detecting whether the buffer has a one-bank or two-bank structure in advance, the control circuit can pre-set the appropriate timing parameters for data latching and address counting, enabling optimal clock frequency selection without requiring complex real-time adjustments during operation.
4Manufacturing precision
If fixed data latch timing is used, then manufacturing precision requirements are reduced, but read operation speed cannot be optimized for different buffer configurations
Solution Approach 1:
The patent implements variable timing parameters for data latching based on the detected bank structure. Instead of using fixed timing that would simplify manufacturing, the system adjusts the data latch timing parameter dynamically, allowing optimal read speed for both one-bank and two-bank buffer configurations while maintaining reasonable manufacturing precision requirements.
Data Source
AI summary
A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.