Semiconductor Memory ECC Buffering for High-Speed Data Reliability
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Solution Overview
Problem
As semiconductor devices increase in operating speed, such as with DDR2 or DDR3 signaling, the probability of errors during data transmission also increases, necessitating a reliable method for error detection and correction to ensure data integrity.
Innovation Solution
A semiconductor system with separate registers for storing corrected internal data generated by successive error correction operations, allowing continuous input and output of data and parity through shared data and parity lines, enabling error correction and data merging while maintaining reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of semiconductor devices is increased to improve productivity, then the data transmission speed increases, but the probability of errors during data transmission increases, worsening reliability
Solution Approach 1:
The patent applies preliminary action by performing error correction operations in advance before data is actually needed. The system stores corrected data in buffers after correcting errors from previously read data, so that when data is requested, the corrected version is already available. This allows high-speed data transmission while maintaining reliability through pre-performed error correction.
Solution Approach 2:
The patent uses buffers as intermediary elements between the memory cells and the output. These buffers temporarily store both erroneous and corrected data, allowing the error correction process to occur asynchronously without blocking the high-speed data transmission flow. The intermediary buffers decouple the error correction operation from the data output timing.
2Reliability
If separate error correction operations are performed for different data sets, then data integrity is improved, but the device complexity increases due to multiple registers and correction circuits
Solution Approach 1:
The patent applies universality by designing a single error correction circuit that can handle multiple different data sets sequentially. The same correction circuit corrects errors for first data, stores the corrected version, then corrects errors for second data, and so on. This multi-functional approach maintains data integrity through separate correction operations while avoiding the need for dedicated correction circuits for each data set, thus reducing overall device complexity.
Solution Approach 2:
The patent merges the error correction functionality with the existing memory read operation. The correction circuit is integrated into the memory device itself, and the correction process is combined with the normal data retrieval and buffering operations. This consolidation achieves separate error correction for different data sets without adding significant structural complexity, as the correction function is merged with existing components.
3Reliability
If error correction code is transmitted with data to ensure reliability, then data transmission reliability improves, but the loss of time increases due to additional transmission overhead
Solution Approach 1:
The patent performs error correction in advance during the data read operation itself, before the data needs to be transmitted. By correcting errors and storing corrected data in buffers during the read phase, the system eliminates the need for separate error correction transmission overhead during data output, thus maintaining reliability without adding transmission time.
Solution Approach 2:
The memory device performs error correction on its own during the data read operation, without requiring external correction codes or separate correction transmissions. The self-service error correction occurs internally as data is being read and buffered, eliminating the time loss associated with transmitting and processing separate error correction information.
Data Source
AI summary
A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a command and an address, and inputting/outputting data. The semiconductor system may include a second semiconductor device including first and second registers, wherein first corrected data, which is generated by correcting an error of internal data outputted in a first error correction operation, may be stored in the first register, and second corrected data, which is generated by correcting an error of the internal data outputted in a second error correction operation, may be stored in the second register, based on the command and the address.