Semiconductor Memory Devices With ECC Encoding And Decoding
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Solution Overview
Problem
The increasing bit errors and decreasing yield of dynamic random-access memory (DRAM) due to shrinking fabrication design rules pose challenges in maintaining high-speed operation and cost efficiency.
Innovation Solution
A semiconductor memory device incorporating a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit that performs s-bit ECC encoding and t-bit ECC decoding to correct errors, enhancing data reliability and storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are shrunk to increase storage capacity, then storage density is improved, but bit error rate increases and yield decreases
Solution Approach 1:
The patent applies preliminary action by performing ECC encoding on data before it is written to the memory cell array. The control logic circuit generates check bits from the data to be stored and encodes them together with the original data, creating a codeword that includes both data bits and check bits. This preliminary error correction preparation allows the memory system to detect and correct bit errors that occur during storage, thereby maintaining reliability despite shrunk fabrication design rules that increase storage density.
2Quantity of substance
If fabrication design rules are shrunk to increase storage capacity, then storage density is improved, but manufacturing yield decreases
Solution Approach 1:
The patent applies parameter changes by modifying the data structure parameters - specifically, by adding check bits to the original data to create extended codewords. The control logic circuit changes the parameter configuration from simple data storage to encoded data storage with integrated error correction capabilities. This parameter transformation allows the memory device to maintain high manufacturing yield by correcting defects introduced during shrinkage-based scaling, thereby improving ease of manufacture despite reduced fabrication design rules.
3Reliability
If ECC encoding is performed on all data, then error correction capability is improved, but processing time increases
Solution Approach 1:
The patent applies partial action by implementing ECC encoding selectively rather than uniformly on all data operations. The control logic circuit determines whether to perform full s-bit ECC encoding or reduced t-bit ECC decoding based on the specific operation requirements. For write operations, full s-bit encoding is applied to maximize error protection, while for read operations, the system can perform lighter t-bit decoding when full error correction is not required. This partial application of ECC operations reduces processing time while maintaining adequate error correction capability for critical operations.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.