Semiconductor Memory ECC Engine Circuit Error Management
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Solution Overview
Problem
The increasing bit errors and decreasing yield of DRAMs due to shrinking fabrication design rules lead to a need for effective error correction mechanisms in semiconductor memory devices.
Innovation Solution
Incorporating an error correction code (ECC) engine circuit, error information register, and control logic circuit in semiconductor memory devices to perform ECC decoding, generate error signals, and skip encoding/decoding operations on memory cell rows with permanent faults, thereby reducing uncorrectable errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM fabrication design rules are shrunk to improve integration density, then manufacturing capacity increases, but bit error rate increases and yield decreases
Solution Approach 1:
The memory array is divided into multiple banks, and each bank is further divided into multiple sub-arrays. This segmentation allows selective operation of affected regions while maintaining functionality of other regions, thereby managing bit errors in specific locations without compromising the entire memory device.
Solution Approach 2:
Redundant memory cells and redundant word lines are introduced as intermediary elements to replace defective memory cells and word lines. The redundant components serve as backup resources that can be activated when errors are detected in primary components, thereby maintaining memory reliability despite fabrication defects.
2Quantity of substance
If DRAM fabrication design rules are shrunk to improve integration density, then manufacturing capacity increases, but yield decreases
Solution Approach 1:
The system dynamically changes operational parameters by selectively enabling or disabling specific banks and sub-arrays based on detected error patterns. This parameter change allows the memory device to adapt to fabrication variations and maintain acceptable yield by optimizing the usage of available functional resources.
Solution Approach 2:
Redundant word lines and memory cells are pre-configured during manufacturing to potential defect locations. This preliminary action ensures that backup resources are ready before actual errors occur, enabling rapid response to bit errors without requiring complex real-time reconfiguration.
3Reliability
If ECC decoding is performed on all memory cell rows, then error detection capability is maximized, but processing time and complexity increase
Solution Approach 1:
ECC decoding is applied selectively to specific banks and sub-arrays based on detected error patterns rather than uniformly across the entire memory array. This local quality approach concentrates error correction resources on affected regions, improving error detection efficiency while reducing overall processing complexity.
Solution Approach 2:
The memory array is divided into multiple banks and sub-arrays, allowing independent ECC decoding operations on segmented regions. This segmentation enables parallel processing of error correction for different regions, reducing overall processing time and complexity compared to sequential decoding of the entire array.
4Reliability
If ECC operations are performed on all memory cell rows, then error correction is comprehensive, but operation speed decreases
Solution Approach 1:
The memory array is divided into multiple banks and sub-arrays that can be operated independently. ECC operations are performed only on actively accessed or error-prone segments rather than the entire array, thereby maintaining error correction effectiveness while significantly improving operation speed through reduced processing scope.
Solution Approach 2:
Instead of performing ECC operations on all memory cell rows, the system applies ECC decoding only to specific sub-arrays or banks where errors are detected or where data is being accessed. This partial action approach maintains sufficient error correction capability while avoiding the performance penalty of universal ECC processing.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine circuit, an error information register and a control logic circuit. The memory cell array includes memory cell rows. The control logic circuit controls the ECC engine circuit to generate an error generation signal based on performing a first ECC decoding on first sub-pages in a first memory cell row in a scrubbing operation and based on performing a second ECC decoding on second sub-pages in a second memory cell row in a normal read operation on the second memory cell row. The control logic circuit records error information in the error information register and controls the ECC engine circuit to skip an ECC encoding and an ECC decoding on a selected memory cell row of the first memory cell row and the second memory cell row based on the error information.